FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 192

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.16.2
5.16.2.1
192
Data Transfers to/from Main Memory
The following sections describe the details on how HCD and the ICH4 communicate via the
Schedule data structures. The discussion is organized in a top-down manner, beginning with the
basics of walking the Frame List, followed by a description of generic processing steps common to
all transfer descriptors, and finally a discussion on Transfer Queuing.
Executing the Schedule
Software programs the ICH4 with the starting address of the Frame List and the Frame List index,
then causes the ICH4 to execute the schedule by setting the Run/Stop bit in the Control register to
Run. The ICH4 processes the schedule one entry at a time: the next element in the frame list is not
fetched until the current element in the frame list is retired.
Schedule execution proceeds in the following fashion:
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The ICH4 first fetches an entry from the Frame List. This entry has three fields. Bit 0 indicates
whether the address pointer field is valid. Bit 1 indicates whether the address points to a
Transfer Descriptor or to a queue head. The third field is the pointer itself.
If isochronous traffic is to be moved in a given frame, the Frame List entry points to a Transfer
Descriptor. If no isochronous data is to be moved in that frame, the entry points to a queue
head or the entry is marked invalid and no transfers are initiated in that frame.
If the Frame List entry indicates that it points to a Transfer Descriptor, the ICH4 fetches the
entry and begins the operations necessary to initiate a transaction on USB. Each TD contains a
link field that points to the next entry, as well as indicating whether it is a TD or a QH.
If the Frame List entry contains a pointer to a QH, the ICH4 processes the information from
the QH to determine the address of the next data object that it should process.
The TD/QH process continues until the millisecond allotted to the current frame expires. At
this point, the ICH4 fetches the next entry from the Frame List. If the ICH4 is not able to
process all of the transfer descriptors during a given frame, those descriptors are retired by
software without having been executed.
Intel
®
82801DBM ICH4-M Datasheet