FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 432

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FW82801DBM S L6DN

Manufacturer Part Number
FW82801DBM S L6DN
Description
Manufacturer
Intel
Datasheet

Specifications of FW82801DBM S L6DN

Lead Free Status / RoHS Status
Not Compliant
USB UHCI Controllers Registers
11.2.3
11.2.4
432
USBINTR—Interrupt Enable Register
I/O Offset:
Default Value:
This register enables and disables reporting of the corresponding interrupt to the software. When a
bit is set and the corresponding interrupt is active, an interrupt is generated to the host. Fatal errors
(Host Controller Processor Error-bit 4, USBSTS Register) cannot be disabled by the host
controller. Interrupt sources that are disabled in this register still appear in the Status Register to
allow the software to poll for events.
FRNUM—Frame Number Register
I/O Offset:
Default Value:
Bits [10:0] of this register contain the current frame number which is included in the frame SOF
packet. This register reflects the count value of the internal frame number counter. Bits [9:0] are
used to select a particular entry in the Frame List during scheduled execution. This register is
updated at the end of each frame time.
This register must be written as a word. Byte writes are not supported. This register cannot be
written unless the Host Controller is in the STOPPED state as indicated by the HCHalted bit
(USBSTS register). A write to this register while the Run/Stop bit is set (USBCMD register) is
ignored.
15:11
15:4
10:0
Bit
Bit
3
2
1
0
Reserved
Short Packet Interrupt Enable — R/W.
0 = Disabled.
1 = Enabled.
Interrupt On Complete (IOC) Enable — R/W.
0 = Disabled.
1 = Enabled.
Resume Interrupt Enable — R/W.
0 = Disabled.
1 = Enabled.
Timeout/CRC Interrupt Enable — R/W.
0 = Disabled.
1 = Enabled.
Reserved
Frame List Current Index/Frame Number — R/W. Provides the frame number in the SOF Frame.
The value in this register increments at the end of each time frame (approximately every 1 ms). In
addition, bits [9:0] are used for the Frame List current index and correspond to memory address
signals [11:2].
Base + (04
0000h
Base + (06
0000h
05h)
07h)
Description
Description
Attribute:
Size:
Attribute:
Size:
Intel
R/W (Writes must be Word Writes)
16 bits
®
82801DBM ICH4-M Datasheet
R/W
16 bits

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