FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 297

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

8.1.17
8.1.18
8.1.19
Intel
®
82801DBM ICH4-M Datasheet
MEMBASE—Memory Base Register (HUB-PCI—D30:F0)
Offset Address:
Default Value:
This register defines the base of the hub interface to PCI non-prefetchable memory range. Since the
ICH4 will forward all hub interface memory accesses to PCI, the ICH4 will only use this
information for determining when not to accept cycles as a target.
This register must be initialized by the configuration software. For the purpose of address decode,
address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory address range
will be aligned to a 1-MB boundary.
MEMLIM—Memory Limit Register (HUB-PCI—D30:F0)
Offset Address:
Default Value:
This register defines the upper limit of the hub interface to PCI non-prefetchable memory range.
Since the ICH4 will forward all hub interface memory accesses to PCI, the ICH4 will only use this
information for determining when not to accept cycles as a target.
This register must be initialized by the config software. For the purpose of address decode, address
bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address range will be
aligned to a 1-MB boundary.
PREF_MEM_BASE—Prefetchable Memory Base Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
15:4
15:4
15:4
3:0
Bit
3:0
Bit
Bit
3:0
Prefetchable Memory Address Base
memory address range for PCI. These 12 bits correspond to address bits 31:20.
Reserved. RO.
Memory Address Limit — R/W. Defines the top of the memory range for PCI. These 12 bits
correspond to address bits 31:20.
Reserved
Memory Address Base — R/W. Defines the base of the memory range for PCI. These 12 bits
correspond to address bits 31:20.
Reserved
20–21h
FFF0h
22–23h
0000h
24h–25h
0000FFF0h
—
Hub Interface to PCI Bridge Registers (D30:F0)
R/W. Defines the base address of the prefetchable
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
R/W
16 bits
R/W
16 bits
R/W
16 bit
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