FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 351

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

9.5.10
Intel
®
82801DBM ICH4-M Datasheet
Redirection Table
Index Offset:
Default Value:
The Redirection Table has a dedicated entry for each interrupt input pin. The information in the
Redirection Table is used to translate the interrupt manifestation on the corresponding interrupt pin
into an APIC message.
The APIC will respond to an edge triggered interrupt as long as the interrupt is held until after the
acknowledge cycle has begun. Once the interrupt is detected, a delivery status bit internally to the
I/O APIC is set. The state machine will step ahead and wait for an acknowledgment from the APIC
bus unit that the interrupt message was sent over the APIC bus. Only then will the I/O APIC be
able to recognize a new edge on that interrupt pin. That new edge will only result in a new
invocation of the handler if its acceptance by the destination APIC causes the Interrupt Request
Register bit to go from 0 to 1. (In other words, if the interrupt was not already pending at the
destination.)
63:56
55:48
47:17
Bit
16
15
14
13
12
Destination — R/W.
If bit 11 of this entry is 0 [Physical], then bits [59:56] specifies an APIC ID. In this case, bits 63:59
should be programmed by software to 0.
If bit 11 of this entry is 1 [Logical], then bits [63:56] specify the logical destination address of a set
of processors.
Extended Destination ID (EDID) . These bits are only sent to a local APIC when in Processor
System Bus mode. They become bits [11:4] of the address.
Reserved
Mask — R/W.
0 = Not masked: An edge or level on this interrupt pin results in the delivery of the interrupt to the
1 = Masked: Interrupts are not delivered nor held pending. Setting this bit after the interrupt is
Trigger Mode — R/W. This field indicates the type of signal on the interrupt pin that triggers an
interrupt.
0 = Edge triggered.
1 = Level triggered.
Remote IRR — R/W. This bit is used for level-triggered interrupts; its meaning is undefined for
edge-triggered interrupts.
0 = Reset when an EOI message is received from a local APIC.
1 = Set when Local APIC/s accept the level interrupt sent by the I/O APIC.
Interrupt Input Pin Polarity — R/W. This bit specifies the polarity of each interrupt signal
connected to the interrupt pins.
0 = Active high.
1 = Active low.
Delivery Status — RO. This field contains the current status of the delivery of this interrupt.
Writes to this bit have no effect.
0 = Idle. No activity for this interrupt.
1 = Pending. Interrupt has been injected, but delivery is held up due to the APIC bus being busy
destination.
accepted by a local APIC has no effect on that interrupt. This behavior is identical to the
device withdrawing the interrupt before it is posted to the processor. It is software's
responsibility to deal with the case where the mask bit is set after the interrupt message has
been accepted by a local APIC unit but before the interrupt is dispensed to the processor.
or the inability of the receiving APIC unit to accept the interrupt at this time.
10h–11h (vector 0) through
3E–3Fh (vector 23)
Bit 16=1, Bits[15:12]=0.
All other bits undefined
Description
Attribute:
Size:
LPC Interface Bridge Registers (D31:F0)
R/W, RO
64 bits each, (accessed as
two 32 bit quantities)
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