FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 602

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Table A-3. Intel
602
Alternate GPI SMI Enable
Alternate GPI SMI Status
Monitor SMI Status
Device Activity Status
Device Trap Enable
Bus Address Tracker
Bus Cycle Tracker
TCO_RLD: TCO Timer Reload
and Current Value
TCO_TMR: TCO Timer Initial
Value
TCO_DAT_IN: TCO Data In
TCO_DAT_OUT: TCO Data Out
TCO1_STS: TCO Status
TCO2_STS: TCO Status
TCO1_CNT: TCO Control
TCO2_CNT: TCO Control
GPIO Use Select
GPIO Input/Output Select
GPIO Level for Input or Output
GPIO Blink Enable
GPIO Signal Invert
Register Name
GPIOBASE is set in Section 9.1.14, “GPIOBASE—GPIO Base Address (LPC I/F—D31:F0)” on page 9-312
PMBASE is set in Section 9.1.10, “PMBASE—ACPI Base Address (LPC I/F—D31:F0)” on page 9-310
®
ICH4 Variable I/O Registers (Sheet 2 of 6)
0Ah–0Bh
04h–05h
06h–07h
08h–09h
3A–3Bh
0C–0Fh
18–1Bh
2C–2Fh
38–39h
00–03h
04–07h
Offset
4Ch
4Eh
40h
44h
48h
00h
01h
02h
03h
GPIO I/O Registers at GPIOBASE + Offset
TCO I/O Registers at TCOBASE + Offset
TCOBASE = PMBASE + 40h
Section 9.8.3.14, “ALT_GP_SMI_EN—Alternate GPI SMI Enable Register”
on page 9-384
Section 9.8.3.15, “ALT_GP_SMI_STS—Alternate GPI SMI Status Register”
on page 9-384
Section 9.8.3.16, “MON_SMI—Device Monitor SMI Status and Enable
Register” on page 9-384
Section 9.8.3.17, “DEVACT_STS — Device Activity Status Register” on
page 9-385
Section 9.8.3.18, “DEVTRAP_EN— Device Trap Enable Register” on
page 9-386
Section 9.8.3.19, “BUS_ADDR_TRACK— Bus Address Tracker” on
page 9-387
Section 9.8.3.20, “BUS_CYC_TRACK— Bus Cycle Tracker” on page 9-387
Section 9.9.1, “TCO_RLD—TCO Timer Reload and Current Value Register”
on page 9-389
Section 9.9.2, “TCO_TMR—TCO Timer Initial Value Register” on page 9-390
Section 9.9.3, “TCO_DAT_IN—TCO Data In Register” on page 9-390
Section 9.9.4, “TCO_DAT_OUT—TCO Data Out Register” on page 9-390
Section 9.9.5, “TCO1_STS—TCO1 Status Register” on page 9-391
Section 9.9.6, “TCO2_STS—TCO2 Status Register” on page 9-392
Section 9.9.7, “TCO1_CNT—TCO1 Control Register” on page 9-393
Section 9.9.8, “TCO2_CNT—TCO2 Control Register” on page 9-394
Section 9.10.1, “GPIO_USE_SEL—GPIO Use Select Register” on
page 9-397
Section 9.10.2, “GP_IO_SEL—GPIO Input/Output Select Register” on
page 9-397
Section 9.10.3, “GP_LVL—GPIO Level for Input or Output Register” on
page 9-398
Section 9.10.4, “GPO_BLINK—GPO Blink Enable Register” on page 9-398
Section 9.10.5, “GPI_INV—GPIO Signal Invert Register” on page 9-399
Datasheet Location
Intel
®
82801DBM ICH4-M Datasheet
Register Index