FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 6

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

6
5.2
5.3
5.4
5.5
LAN Controller (B1:D8:F0)............................................................................. 78
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
LPC Bridge (with System and Management Functions) (D31:F0) ................. 92
5.3.1
DMA Operation (D31:F0) ............................................................................... 98
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
PCI DMA ...................................................................................................... 102
5.5.1
5.1.6.1
5.1.6.2
LAN Controller Architectural Overview ............................................. 78
5.2.1.1
5.2.1.2
5.2.1.3
LAN Controller PCI Bus Interface ..................................................... 81
5.2.2.1
5.2.2.2
5.2.2.3
5.2.2.4
5.2.2.5
5.2.2.6
5.2.2.7
Serial EEPROM Interface ................................................................. 89
CSMA/CD Unit .................................................................................. 90
5.2.4.1
5.2.4.2
5.2.4.3
5.2.4.4
Media Management Interface ........................................................... 91
TCO Functionality ............................................................................. 91
5.2.6.1
5.2.6.2
LPC Interface .................................................................................... 92
5.3.1.1
5.3.1.2
5.3.1.3
5.3.1.4
5.3.1.5
5.3.1.6
5.3.1.7
5.3.1.8
5.3.1.9
5.3.1.10 Bus Master Cycles ............................................................ 97
5.3.1.11 LPC Power Management .................................................. 97
5.3.1.12 Configuration and ICH4 Implications................................. 97
Channel Priority ................................................................................ 99
5.4.1.1
5.4.1.2
Address Compatibility Mode ............................................................. 99
Summary of DMA Transfer Sizes ................................................... 100
5.4.3.1
Autoinitialize.................................................................................... 100
Software Commands ...................................................................... 101
5.4.5.1
5.4.5.2
5.4.5.3
PCI DMA Expansion Protocol ......................................................... 102
Type 0 to Type 0 Forwarding ............................................ 77
Type 1 to Type 0 Conversion ............................................ 77
Parallel Subsystem Overview............................................ 79
FIFO Subsystem Overview ............................................... 80
Serial CSMA/CD Unit Overview ........................................ 80
Bus Slave Operation ......................................................... 81
Bus Master Operation ....................................................... 83
CLOCKRUN# Signal ......................................................... 86
PCI Power Management ................................................... 86
PCI Reset Signal ............................................................... 87
Wake-Up Events ............................................................... 88
Wake on LAN* (Preboot Wake-Up)................................... 89
Full Duplex ........................................................................ 90
Flow Control ...................................................................... 90
Address Filtering Modifications ......................................... 90
VLAN Support ................................................................... 91
Receive Functionality ........................................................ 91
Transmit Functionality ....................................................... 91
LPC Cycle Types............................................................... 93
Start Field Definition .......................................................... 93
Cycle Type / Direction (CYCTYPE + DIR)......................... 94
Size ................................................................................... 94
SYNC ................................................................................ 94
SYNC Time-Out ................................................................ 95
SYNC Error Indication ....................................................... 95
LFRAME# Usage .............................................................. 96
I/O Cycles.......................................................................... 97
Fixed Priority ..................................................................... 99
Rotating Priority................................................................. 99
Address Shifting When Programmed for 16-Bit I/O Count
by Words ......................................................................... 100
Clear Byte Pointer Flip-Flop ............................................ 101
DMA Master Clear........................................................... 101
Clear Mask Register........................................................ 101
Intel
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82801DBM ICH4-M Datasheet