FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 373

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

9.8.3.3
Intel
®
82801DBM ICH4-M Datasheet
PM1_CNT—Power Management 1 Control Register
I/O Address:
Default Value:
Lockable:
Power Well:
15:14
12:10
9:3
Bit
13
2
1
0
Reserved.
Sleep Enable (SLP_EN) — WO.
Setting this bit causes the system to sequence into the Sleep state defined by the SLP_TYP field.
Sleep Type (SLP_TYP) — R/W. This 3-bit field defines the type of Sleep the system should enter
when the SLP_EN bit is set to 1.
000 = N: Typically maps to S0 state.
001 =Reserved.
010 =Asserts SLP_S1#: Typically maps to S1-M state.
011 =Reserved
100 =Reserved
101 =Suspend-To-RAM. Assert SLP_S1# and SLP_S3#: Typically maps to S3 state.
110 =Suspend-To-Disk. Assert SLP_S1#, SLP_S3#, and SLP_S4#: Typically maps to S4 state.
111 =Soft Off. Assert SLP_S1#, SLP_S3#, SLP_S4#, and SLP_S5#: Typically maps to S5 state.
NOTE: These bits are only reset by RTCRST#.
Reserved.
Global Release (GBL_RLS) — WO.
0 = This bit always reads as 0.
1 = ACPI software writes a 1 to this bit to raise an event to the BIOS. BIOS software has a
Bus Master Reload (BM_RLD) — R/W. This bit is reset to 0 by PCIRST#
0 = Bus master requests will not cause a break from the C3 state.
1 = Enable Bus Master requests (internal, external or AGPBUSY#) to cause a break from the C3
SCI Enable (SCI_EN) — R/W. Selects the SCI interrupt or the SMI# interrupt for various events
including the bits in the PM1_STS register (bit 10, 8, 0), and bits in GPE0_STS.
0 = These events will generate an SMI#.
1 = These events will generate an SCI.
corresponding enable and status bits to control its ability to receive ACPI events.
state.
PMBASE + 04h
(ACPI PM1a_CNT_BLK)
0000h
No
Bits 0
Bits 8
Bits 13
–
–
7: Core,
12: RTC
–
15: Resume
Description
Attribute:
Size:
Usage:
LPC Interface Bridge Registers (D31:F0)
R/W, WO
32-bit
ACPI or Legacy
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