FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 56

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Signal Description
2.14
2.15
2.16
56
Table 2-14. Real Time Clock Interface
Table 2-15. Other Clocks
Table 2-16. Miscellaneous Signals
Real Time Clock Interface
Other Clocks
Miscellaneous Signals
RTCX1
RTCX2
CLK14
CLK48
CLK66
SPKR
RTCRST#
Name
Name
Name
Special
Special
Type
Type
Type
I
I
I
O
I
Oscillator Clock: This clock is used for 8254 timers. It runs at 14.31818 MHz. This
clock is permitted to stop during S1-M (or lower) states.
48 MHz Clock: This clock is used to run the USB controllers. It runs at 48 MHz.
This clock is permitted to stop during S1-M (or lower) states.
66 MHz Clock: This clock is used to run the hub interface. It runs at 66 MHz. This
clock is permitted to stop during S1-M (or lower) states.
Speaker: The SPKR signal is the output of counter 2 and is internally “ANDed”
with Port 61h bit 1 to provide Speaker Data Enable. This signal drives an external
speaker driver device, which in turn drives the system speaker. Upon PCIRST#,
its output state is 0.
NOTE: SPKR is sampled at the rising edge of PWROK as a functional strap. See
RTC Reset: When asserted, this signal resets register bits in the RTC well and
sets the RTC_PWR_STS bit (bit 2 in GEN_PMCON3 register).
NOTES:
1. Clearing CMOS in an ICH4-based platform can be done by using a jumper on
2. Unless entering the XOR Chain Test Mode, the RTCRST# input must always
Crystal Input 1: This signal is connected to the 32.768 kHz crystal.
Crystal Input 2: This signal is connected to the 32.768 kHz crystal.
RTCRST# or GPI, or using SAFEMODE strap. Implementations should not
attempt to clear CMOS by using a jumper to pull VccRTC low.
be high when all other RTC power planes are on.
Section 2.20.1
resistor on SPKR pin.
for more details. There is a weak integrated pull-down
Description
Description
Description
Intel
®
82801DBM ICH4-M Datasheet