FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 97

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

5.3.1.9
5.3.1.10
5.3.1.11
5.3.1.12
Intel
®
82801DBM ICH4-M Datasheet
Note: If the cycle is not claimed by any peripheral (and subsequently aborted), the ICH4 returns a value
Note: The ICH4 does not support LPC Bus Masters performing I/O cycles. LPC Bus Masters should only
Note: The LPC specification defines he LPCPD# protocol where there is at least 30 us from LPCPD#
Note: The ICH4 cannot accept PCI write cycles from PCI-to-PCI bridges or devices with similar
I/O Cycles
For I/O cycles targeting registers specified in the ICH4’s decode ranges, the ICH4 performs I/O
cycles as defined in the LPC specification. These will be 8-bit transfers. If the processor attempts a
16-bit or 32-bit transfer, the ICH4 breaks the cycle up into multiple 8-bit transfers to consecutive
I/O addresses.
of all 1s (FFh) to the processor. This is to maintain compatibility with ISA I/O cycles where pull-up
resistors would keep the bus high if no device responds.
Bus Master Cycles
The ICH4 supports Bus Master cycles and requests (using LDRQ#) as defined in the LPC
specification. The ICH4 has two LDRQ# inputs, and thus, supports two separate bus master
devices. It uses the associated START fields for Bus Master 0 (0010b) or Bus Master 1 (0011b).
perform memory read or memory write cycles.
LPC Power Management
CLKRUN# Protocol
The CLKRUN# protocol is same as the PCI specification. Stopping the PCI clock stops the LPC
clock.
LPCPD# Protocol
Same timings as for SUS_STAT#. Upon driving SUS_STAT# low, LPC peripherals will drive
LDRQ# low or tri-state it. ICH4 will shut off the LDRQ# input buffers. After driving SUS_STAT#
active, the ICH4 drives LFRAME# low, and tri-states (or drive low) LAD[3:0].
assertion to LRST# assertion. This specification explicitly states that this protocol only applies to
entry/exit of low power states (which does not include asynchronous reset events). The ICH4 will
assert the SUS_STAT# (connects to LPCPD#) and PCIRST# connects to LRST#) at the same time
when the core logic is reset (via CF9, PWROK, SYS_RESET#, etc.). This is not inconsistent with
LPC LPCPD# protocol.
Configuration and ICH4 Implications
LPC Interface Decoders
To allow the I/O cycles and memory mapped cycles to go to the LPC interface, the ICH4 includes
several decoders. During configuration, the ICH4 must be programmed with the same decode ranges
as the peripheral. The decoders are programmed via the Device 31:Function 0 configuration space.
characteristics (specifically those with a “Retry Read” feature which is enabled) to an LPC device
if there is an outstanding LPC read cycle towards the same PCI device or bridge. These cycles are
Functional Description
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