FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 141

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

5.12.1
Intel
®
Table 5-34. General Power States for Systems Using Intel
82801DBM ICH4-M Datasheet
Substates
G0/S0/C0
G0/S0/C1
G0/S0/C2
G0/S0/C3
G0/S0/C4
G1/S1-M
Intel
Table 5-34
match the corresponding ACPI states.
G1/S3
G1/S4
G2/S5
State/
G3
®
Full On: Processor operating. Individual devices may be shut down to save power. The different
processor operating levels are defined by Cx states, as shown in
ICH4 can throttle the STPCLK# signal to reduce power consumption. The throttling can be initiated
by software or by the THRM# input signal.
Auto-Halt: Processor has executed a AutoHalt instruction and is not executing code. The processor
snoops the bus and maintains cache coherency.
Quickstart: The STPCLK# signal goes active to the processor. The processor performs a Stop-Grant
cycle, halts its instruction stream, and remains in that state until the STPCLK# signal goes inactive. In
the Quickstart state, the processor snoops the bus and maintains cache coherency.
Stop-Clock: The STPCLK# signal goes active to the processor. The processor performs a Stop-
Grant cycle, halts its instruction stream. ICH4 then asserts STP_CPU#, which forces the clock
generator to stop the processor clock. This is also used for Intel SpeedStep technology support.
Accesses to memory (by AGP, PCI, or internal units) is not permitted while in a C3 state. It is
assumed that the ARB_DIS bit is set prior to entering C3 state.
Stop-Clock with lower Processor voltage. This closely resembles the G0/S0/C3 state. However,
after the ICH4 has asserted STP_CPU#, it then lowers the voltage to the processor. This reduces the
leakage on the processor. Prior to exiting the C4 state, the ICH4 increases the voltage to the
processor.
Powered-On-Suspend (POS): In this state, all clocks (except the 32.768 kHz clock) are stopped.
The system context is maintained in system DRAM. Power is maintained to PCI, the processor,
memory controller, memory, and all other critical subsystems. Note that this state does not preclude
power being removed from non-essential devices (e.g., disk drives).
During this state, the processor can be selected for either Deep Sleep or Deeper Sleep.
In Deeper Sleep, the processor voltage is reduced in this state to reduce the leakage power.
Suspend-To-RAM (STR): The system context is maintained in system DRAM, but power is shut off
to non-critical circuits. Memory is retained, and refreshes continue. All clocks stop except RTC clock.
Suspend-To-Disk (STD): The context of the system is maintained on the disk. All power is then shut
off to the system except for the logic required to resume.
Soft Off (SOFF): System context is not maintained. All power is shut off except for the logic required
to restart. A full boot is required when waking.
Mechanical OFF (MOFF): System context not maintained. All power is shut off except for the RTC.
No “Wake” events are possible, because the system does not have any power. This state occurs if
the user removes the batteries, turns off a mechanical switch, or if the system power supply is at a
level that is insufficient to power the “waking” logic. When system power returns, transition will
depends on the state just prior to the entry to G3 and the AFTERG3 bit in the GEN_PMCON3 register
(D31:F0, offset A4). Refer to
ICH4 and System Power States
shows the power states defined for ICH4-based platforms. The state names generally
Table 5-42
Legacy Name / Description
for more details.
®
ICH4
Table
5-35. Within the C0 state, the
Functional Description
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