FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 206

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.16.7
5.16.8
206
Table 5-74. Bits Maintained in Low Power States
Note: The scheme described below assumes that the keyboard controller (8042 or equivalent) is on the
USB Power Management
The Host Controller can be put into a suspended state and its power can be removed. This requires
that certain bits of information are retained in the resume power plane of the ICH4 so that a device
on a port may wake the system. Such a device may be a fax-modem, which will wake up the
machine to receive a fax or take a voice message. The settings of the following bits in I/O space
will be maintained when the ICH4 enters the S3, S4 or S5 states:
When the ICH4 detects a resume event on any of its ports, it will set the corresponding USB_STS
bit in ACPI space. If USB is enabled as a wake/break event, the system will wake up and an SCI
will be generated.
USB Legacy Keyboard Operation
When a USB keyboard is plugged into the system, and a standard keyboard is not, the system may
not boot, and DOS legacy software will not run, because the keyboard will not be identified. The
ICH4 implements a series of trapping operations which will snoop accesses that go to the keyboard
controller, and put the expected data from the USB keyboard into the keyboard controller.
LPC bus.
This legacy operation is performed through SMM space.
path. The latched SMI source (60R, 60W, 64R, 64W) is available in the Status Register. Because
the enable is after the latch, it is possible to check for other events that didn't necessarily cause an
SMI. It is the software's responsibility to logically AND the value with the appropriate enable bits.
Note also that the SMI is generated before the PCI cycle completes (e.g., before TRDY# goes
active) to ensure that the processor does not complete the cycle before the SMI is observed. This
method is used on MPIIX and has been validated.
The logic will also need to block the accesses to the 8042. If there is an external 8042, then this is
simply accomplished by not activating the 8042 CS. This is simply done by logically ANDing the
4 enables (60R, 60W, 64R, 64W) with the 4 types of accesses to determine if 8042CS should go
active. An additional term is required for the “Pass-through” case.
The state table for the diagram is shown in
Port Status and Control
Command
Register
Status
10h & 12h
Offset
00h
02h
Bit
12
3
2
2
6
8
Table
Enter Global Suspend Mode (EGSM)
Resume Detect
Port Enabled/Disabled
Resume Detect
Low Speed Device Attached
Suspend
5-75.
Figure 5-19
Intel
®
Description
82801DBM ICH4-M Datasheet
shows the Enable and Status