FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 416

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

IDE Controller Registers (D31:F1)
10.2.2
416
BMIS[P,S]—Bus Master IDE Status Register
Address Offset:
Default Value:
Bit
4:3
7
6
5
2
1
0
Interrupt Status - R/WC
0 = This bit is cleared by software writing ‘1’ to the bit position. If this bit is cleared while the interrupt is
still active, this bit will remain clear until another assertion edge is detected on the interrupt line
1 = This bit is set when the host controller executes a PRD that has the PRD_INT bit set. When this bit
is cleared by software, the interrupt is cleared.
Drive 1 DMA Capable — R/W.
0 = Not Capable.
1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that drive 1 for this
Drive 0 DMA Capable — R/W.
0 = Not Capable
1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that drive 0 for this
Reserved. Returns 0s.
Interrupt — R/WC. Software can use this bit to determine if an IDE device has asserted its interrupt
line (IRQ 14 for the Primary channel, and IRQ 15 for Secondary).
0 = This bit is cleared by software writing a 1 to the bit position. If this bit is cleared while the interrupt
1 = Set by the rising edge of the IDE interrupt line, regardless of whether or not the interrupt is
Error — R/WC.
0 = This bit is cleared by software writing a 1 to the bit position.
1 = This bit is set when the controller encounters a target abort or master abort when transferring
Bus Master IDE Active (ACT) — RO.
0 = This bit is cleared by the ICH4 when the last transfer for a region is performed, where EOT for
1 = Set by the ICH4 when the Start bit is written to the Command register.
channel is capable of DMA transfers, and that the controller has been initialized for optimum
performance. The ICH4 does not use this bit. It is intended for systems that do not attach BMIDE
to the PCI bus.
channel is capable of DMA transfers, and that the controller has been initialized for optimum
performance. The ICH4 does not use this bit. It is intended for systems that do not attach BMIDE
to the PCI bus.
is still active, this bit will remain clear until another assertion edge is detected on the interrupt line.
masked in the 8259 or the internal I/O APIC. When this bit is read as a 1, all data transferred from
the drive is visible in system memory.
data on PCI.
that region is set in the region descriptor. It is also cleared by the ICH4 when the Start bit is
cleared in the Command register. When this bit is read as a 0, all data transferred from the drive
during the previous bus master command is visible in system memory, unless the bus master
command was aborted.
Primary: 02h
Secondary: 0Ah
00h
Description
Attribute:
Size:
Intel
R/WC, R/W, RO
8 bits
®
82801DBM ICH4-M Datasheet