FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 527

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

15.2.5
15.2.6
Intel
®
82801DBM ICH4-M Datasheet
x_PICB—Position in Current Buffer Register
I/O Address:
Default Value:
Lockable:
Software can read the registers at the offsets 08h, 0Ah, and 0Bh by performing a 32-bit read from
the address offset 08h. Software can also read this register individually by doing a single, 16-bit
read to offset 08h. Reads across DWord boundaries are not supported.
x_PIV—Prefetch Index Value Register
I/O Address:
Default Value:
Lockable:
Software can read the registers at the offsets 08h, 0Ah, and 0Bh by performing a 32-bit read from
the address offset 08h. Software can also read this register individually by doing a single, 8-bit read
to offset 0Ah. Reads across DWord boundaries are not supported.
15:0
Bit
Bit
7:5
4:0
Position In Current Buffer [15:0] — RO. These bits represent the number of samples left to be
processed in the current buffer.
Hardwired to 0
Prefetched Index Value [4:0] — RO. These bits represent which buffer descriptor in the list has
been prefetched.
MBAR + 08h (MIPICB),
MBAR + 18h (MOPICB),
0000h
No
MBAR + 0Ah (MIPIV),
MBAR + 1Ah (MOPIV)
00h
No
Description
Description
AC ’97 Modem Controller Registers (D31:F6)
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
RO
16 bits
Core
RO
8 bits
Core
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