FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 496

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

AC ’97 Audio Controller Registers (D31:F5)
14.1.13
14.1.14
496
MBBAR—Bus Master Base Address Register
(Audio—D31:F5)
Address Offset:
Default Value:
Lockable:
This BAR creates 256-bytes of memory space to signify the base address of the bus master
memory space. The lower 64-bytes of the space pointed to by this register point to the same
registers as the MBBAR.
SVID—Subsystem Vendor ID Register (Audio—D31:F5)
Address Offset:
Default Value:
Lockable:
The SVID register, in combination with the Subsystem ID register, enable the operating
environment to distinguish one audio subsystem from the other(s). This register is implemented as
write-once register. Once a value is written to it, the value can be read back. Any subsequent writes
will have no effect.
This register is not affected by the D3
15:0
Bit
31:8
Bit
7:3
2:1
0
Subsystem Vendor ID — R/Write-Once.
Base Address — R/W. I/O offset to use for decoding the PCM In, PCM Out, and Microphone 1
DMA engines.
Reserved. Read as 0s.
Type — RO. Indicates the base address exists in 32-bit address space
Resource Type Indicator (RTE) — RO. This bit is set to 0, indicating a request for memory space.
00000000h
0000h
1C
No
2D
No
–
–
1Fh
2Ch
HOT
to D0 transition.
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Intel
®
82801DBM ICH4-M Datasheet
R/W, RO
32 bits
Core
R/WO
16 bits
Core