FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 96

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.3.1.8
96
Figure 5-7. Typical Timing for LFRAME#
Figure 5-8. Abort Mechanism
LFRAME# Usage
Start of Cycle
For Memory, I/O, and DMA cycles, the ICH4 asserts LFRAME# for 1 clock at the beginning of the
cycle
Abort Mechanism
When performing an Abort, the ICH4 drives LFRAME# active for four consecutive clocks. On the
fourth clock, it drives LAD[3:0] to 1111b.
The ICH4 performs an abort for the following cases (possible failure cases):
•
•
•
•
LFRAME#
LFRAME#
LAD[3:0]
LAD[3:0]
ICH4 starts a Memory, I/O, or DMA cycle, but no device drives a valid SYNC after four
consecutive clocks.
ICH4 starts a Memory, I/O, or DMA cycle, and the peripheral drives an invalid SYNC pattern.
A peripheral drives an illegal address when performing bus master cycles.
A peripheral drives an invalid value.
(Figure
LCLK
LCLK
5-7). During that clock, the ICH4 drives LAD[3:0] with the proper START field.
Start
Start
Clock
1
CYCTYPE
Dir & Size
CYCTYPE
Dir & Size
ADDR
ADDR
Clocks
1 - 8
TAR
TAR
Clocks
Syncs causes
Too many
2
Sync
timeout
Clocks
Sync
1 - n
Intel
Peripheral must
Clocks
®
stop driving
Data
82801DBM ICH4-M Datasheet
2
TAR
Clocks
2
Start
Clock
Chipset will
drive high
1