FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 431

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

11.2.2
Intel
®
82801DBM ICH4-M Datasheet
USBSTS—USB Status Register
I/O Offset:
Default Value:
This register indicates pending interrupts and various states of the Host Controller. The status
resulting from a transaction on the serial bus is not indicated in this register. Software sets a bit to 0
in this register by writing a 1 to it.
15:6
Bit
5
4
3
2
1
0
Reserved
HCHalted — R/WC.
0 = Software resets this bit to 0 by writing a 1 to the bit position.
1 = The Host Controller has stopped executing as a result of the Run/Stop bit being set to 0, either
Host Controller Process Error — R/WC.
0 = Software resets this bit to 0 by writing a 1 to the bit position.
1 = The Host Controller has detected a fatal error. This indicates that the Host Controller suffered
Host System Error — R/WC.
0 = Software resets this bit to 0 by writing a 1 to the bit position.
1 = A serious error occurred during a host system access involving the Host Controller module. In
Resume Detect (RSM_DET) — R/WC.
0 = Software resets this bit to 0 by writing a 1 to the bit position.
1 = The Host Controller received a “RESUME” signal from a USB device. This is only valid if the
USB Error Interrupt — R/WC.
0 = Software resets this bit to 0 by writing a 1 to the bit position.
1 = Completion of a USB transaction resulted in an error condition (e.g., error counter underflow).
USB Interrupt (USBINT) — R/WC.
0 = Software resets this bit to 0 by writing a 1 to the bit position.
1 = The Host Controller sets this bit when the cause of an interrupt is a completion of a USB
by software or by the Host Controller hardware (debug mode or an internal error). Default.
a consistency check failure while processing a Transfer Descriptor. An example of a
consistency check failure would be finding an illegal PID field while processing the packet
header portion of the TD. When this error occurs, the Host Controller clears the Run/Stop bit in
the Command register to prevent further schedule execution. A hardware interrupt is
generated to the system.
a PCI system, conditions that set this bit to 1 include PCI Parity error, PCI Master Abort, and
PCI Target Abort. When this error occurs, the Host Controller clears the Run/Stop bit in the
Command register to prevent further execution of the scheduled TDs. A hardware interrupt is
generated to the system.
Host Controller is in a global suspend state (bit 3 of Command register = 1).
If the TD on which the error interrupt occurred also had its IOC bit set, both this bit and Bit 0
are set.
transaction whose Transfer Descriptor had its IOC bit set. Also set when a short packet is
detected (actual length field in TD is less than maximum length field in TD), and short packet
detection is enabled in that TD.
Base + (02
0020h
–
03h)
Description
Attribute:
Size:
USB UHCI Controllers Registers
R/WC
16 bits
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