FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 318

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FW82801DBM S L6DN

Manufacturer Part Number
FW82801DBM S L6DN
Description
Manufacturer
Intel
Datasheet

Specifications of FW82801DBM S L6DN

Lead Free Status / RoHS Status
Not Compliant
LPC Interface Bridge Registers (D31:F0)
9.1.23
318
GEN_STA—General Status Register (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
7:3
Bit
2
1
0
Reserved
SAFE_MODE — RO.
0 = ICH4 sampled AC_SDOUT low on the rising edge of PWROK.
1 = ICH4 sampled AC_SDOUT high on the rising edge of PWROK. ICH4 will force
NO_REBOOT — R/W-Special.
0 = Normal TCO Timer reboot functionality (reboot after 2nd TCO timeout). This bit cannot be set to
1 = ICH4 will disable the TCO Timer system reboot feature. This bit is set either by hardware when
Reserved
FREQ_STRAP[3:0] bits to all 1s (safe mode multiplier).
0 by software if the strap is set to No Reboot.
SPKR is sampled high on the rising edge of PWROK, or by software writing a 1 to the bit.
D4h
0Xh
No
Description
Attribute:
Size:
Power Well:
Intel
®
82801DBM ICH4-M Datasheet
RO, R/W-Special
8 bit
Core

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