FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 168

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.13.1.3
5.13.1.4
5.13.2
168
Note: The INTRD_DET bit resides in the ICH4’s RTC well, and is set and cleared synchronously with
Note: If the INTRUDER# signal is still active when software attempts to clear the INTRD_DET bit, the
If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is written as a 1,
then the INTRD_DET signal will go to a 0 when INTRUDER# input signal goes inactive. Note
that this is slightly different than a classic sticky bit, since most sticky bits would remain active
indefinitely when the signal goes active and would immediately go inactive when a 1 is written to
the bit.
the RTC clock. Thus, when software attempts to clear INTRD_DET (by writing a 1 to the bit
location) there may be as much as two RTC clocks (about 65 µs) delay before the bit is actually
cleared. Also, the INTRUDER# signal should be asserted for a minimum of 1 ms to guarantee that
the INTRD_DET bit will be set.
bit will remain set and the SMI will be generated again immediately. The SMI handler can clear the
INTRD_SEL bits to avoid further SMIs. However, if the INTRUDER# signal goes inactive and
then active again, there will not be further SMIs, since the INTRD_SEL bits would select that no
SMI# be generated.
Detecting Improper FWH Programming
The ICH4 can detect the case where the FWH is not programmed. This results in the first
instruction fetched to have a value of FFh. If this occurs, the ICH4 sets the BAD_BIOS bit, which
can then be reported via the Heartbeat and Event reporting using an external, Alert on LAN
enabled LAN Controller (See
Handling an ECC Error or Other Memory Error
The Host Controller provides a message to indicate that it would like to cause an SMI#, SCI,
SERR#, or NMI. The software must check the Host Controller as to the exact cause of the error.
Alert on LAN*
The ICH4 integrated LAN controller supports Alert on LAN functionality when used with the
82562EM Platform LAN Connect component. This allows the integrated LAN controller to report
messages to a network management console without the aid of the system processor. This is crucial
in cases where the processor is malfunctioning or cannot function due to being in a low-power
state.
The ICH4 also features an independent, dedicated SMBus interface, referred to as the SMLINK
interface that can be used with an external Alert on LAN (or Alert on LAN 2) enabled LAN
Controller. This separate interface is required, since devices on the system SMBus will be powered
down during some low power states.
The basic scheme is for the ICH4 integrated LAN Controller to send a prepared Ethernet message
to a network management console. The prepared message is stored in the non-volatile EEPROM
that is connected to the ICH4.
Messages will be sent by the LAN Controller either because a specific event has occurred, or they
will be sent periodically (also known as a heartbeat). The event and heartbeat messages have the
exact same format. The event messages are sent based on events occurring. The heartbeat messages
is sent every 30 to 32 seconds. When an event occurs, the ICH4 sends a new message and
increments the SEQ[3:0] field. For heartbeat messages, the sequence number does not increment.
Section
5.13.2).
Intel
®
82801DBM ICH4-M Datasheet