FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 146

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
146
Table 5-38. Break Events
A C1, C2, C3, or C4 state ends due to a Break event. Based on the break event, the ICH4 returns
the system to C0 state.
events from C1 are indicated in the processor’s datasheet.
The ICH4 supports the Pending Break Event (PBE) indication from the processor using the FERR#
signal. The following rules apply:
The break event associated with this new mechanism does not need to set any particular status bit,
since the pending interrupt will be serviced by the processor after returning to the C0 state.
Any unmasked interrupt goes active
Any internal event that will cause an
NMI or SMI#
Any internal event that will cause
INIT# to go active
Any bus master request (internal,
external or DMA) goes active and
BM_RLD=1
Processor Pending Break Event
Indication
1. When STPCLK# is detected active by the processor, the FERR# signal from the processor will
2. When the ICH4 asserts STPCLK#, it will latch the current state of the FERR# signal and
3. When the ICH4 detects the Stop-Grant cycle, it will start looking at the FERR# signal as a
4. When the processor detects the deassertion of STPCLK#, the processor will start driving the
5. The ICH4 waits at least 180 ns after deasserting STPCLK# and then starts using the FERR#
be redefined to indicate whether an interrupt is pending. The signal is active low (i.e., FERR#
will be low to indicate a pending interrupt).
continue to present this state to the FERR# state machine (independent of what the FERR# pin
does after the latching).
break event indication. If FERR# is sampled low, a break event is indicated. This will force a
transition to the C0 state.
FERR# signal with the natural value (i.e., the value it would do if the pin was not muxed). The
time from STPCLK# inactive to the FERR# signal transition back to the native function must
be less than 120 ns.
signal for an indication of a floating point error. The maximum time that the ICH4 may wait is
bounded such that it must have a chance to look at the FERR# signal before reasserting
STPCLK#. Based on current implementation, that maximum time would be 240 ns (8 PCI
clocks).
Event
Table 5-38
lists the possible break events from C2, C3, or C4. The break
Breaks from
C2, C3, C4
C2, C3, C4
C2, C3, C4
C2, C3, C4
C3, C4
IRQ[0:15] when using the 8259s, IRQ[0:23] for
I/O APIC. Since SCI is an interrupt, any SCI will
also be a break event.
Many possible sources
Could be indicated by the keyboard controller
via the RCIN input signal.
Need to wake up processor so it can do snoops.
Only available if FERR# enabled for break event
indication (See GEN_CNTL.FERR# Mux-En bit
in
Section
Intel
9.1.22).
®
82801DBM ICH4-M Datasheet
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