FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 298

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.20
8.1.21
8.1.22
8.1.23
298
PREF_MEM_MLT—Prefetchable Memory Limit Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
IOBASE_HI—I/O Base Upper 16 Bits Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
IOLIM_HI—I/O Limit Upper 16 Bits Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
INT_LINE—Interrupt Line Register (HUB-PCI—D30:F0)
Offset Address:
Default Value:
15:4
Bit
7:0
15:0
15:0
3:0
Bit
Bit
Bit
Interrupt Line (INT_LN) — RO. Hardwired to 00h. The bridge does not generate interrupts, and
interrupts from downstream devices are routed around the bridge.
Prefetchable Memory Address Limit
address range for PCI. These 12 bits correspond to address bits 31:20.
Reserved. RO
I/O Address Base Upper 16 Bits [31:16] — RO. Not supported; hardwired to 0.
I/O Address Limit Upper 16 Bits [31:16] — RO. Not supported; hardwired to 0.
26h–27h
00000000h
30–31h
0000h
32–33h
0000h
3Ch
00h
—
RW. Defines the limit address of the prefetchable memory
Description
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Intel
®
82801DBM ICH4-M Datasheet
R/W
16 bit
RO
16 bits
RO
16 bits
RO
8 bits