FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 278

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

LAN Controller Registers (B1:D8:F0)
7.2.2
278
System Control Block Command Word Register
Offset Address:
Default Value:
The processor places commands for the Command and Receive units in this register. Interrupts are
also acknowledged in this register.
Bit
15
14
13
12
10
11
9
8
CX Mask — R/W.
0 = Interrupt not masked.
1 = Disable the generation of a CX interrupt.
FR Mask — R/W.
0 = Interrupt not masked.
1 = Disable the generation of an FR interrupt.
CNA Mask — R/W.
0 = Interrupt not masked.
1 = Disable the generation of a CNA interrupt.
RNR Mask — R/W.
0 = Interrupt not masked.
1 = Disable the generation of an RNR interrupt.
ER Mask — R/W.
0 = Interrupt not masked.
1 = Disable the generation of an ER interrupt.
FCP Mask — R/W.
0 = Interrupt not masked.
1 = Disable the generation of an FCP interrupt.
Software Generated Interrupt (SI) — WO.
0 = No Effect.
1 = Setting this bit causes the LAN Controller to generate an interrupt.
Interrupt Mask (IM) — R/W. This bit enables or disables the LAN Controller’s assertion of the
INTA# signal. This bit has higher precedence that the Specific Interrupt Mask bits and the SI bit.
0 = Enable the assertion of INTA#.
1 = Disable the assertion of INTA#.
02
0000h
–
03h
Description
Attribute:
Size:
Intel
®
82801DBM ICH4-M Datasheet
R/W
16 bits