FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 232

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
l
232
Table 5-87. Block Read/Write Protocol without PEC
Note: For Block Write, if the I
When programmed for a block write command, the Transmit Slave Address, Device Command,
and Data0 (count) registers are sent. Data is then sent from the Block Data Byte register; the total
data sent being the value stored in the Data0 Register. On block read commands, the first byte
received is stored in the Data0 register, and the remaining bytes are stored in the Block Data Byte
register.
The format of the Block Read/Write protocol is shown in
will still send the number of bytes (on writes) or receive the number of bytes (on reads) indicated in
the DATA0 register. However, it will not send the contents of the DATA0 register as part of the
message.
11–18
20–27
29–36
38–45
2–8
Bit
10
19
28
37
46
...
...
...
...
1
9
Start
Slave Address - 7 bits
Write
Acknowledge from slave
Command code - 8 bits
Acknowledge from slave
Byte Count - 8 bits
Acknowledge from Slave
Data Byte 1 - 8 bits
Acknowledge from Slave
Data Byte 2 - 8 bits
Acknowledge from slave
Data Bytes / Slave
Acknowledges...
Data Byte N - 8 bits
Acknowledge from Slave
Stop
Block Write Protocol
2
Description
C_EN bit is set, the format of the command changes slightly. The ICH4
21–27
30–37
39–46
48–55
11–18
2–8
Bit
10
19
20
28
29
38
47
56
...
...
...
...
1
9
Table 5-87
Start
Slave Address - 7 bits
Write
Acknowledge from slave
Command code - 8 bits
Acknowledge from slave
Repeated Start
Slave Address - 7 bits
Read
Acknowledge from slave
Byte Count from slave - 8 bits
Acknowledge
Data Byte 1 from slave - 8 bits
Acknowledge
Data Byte 2 from slave - 8 bits
Acknowledge
Data Bytes from slave/Acknowledge
Data Byte N from slave - 8 bits
NOT Acknowledge
Stop
Intel
Block Read Protocol
®
82801DBM ICH4-M Datasheet
and
Table
Description
5-88.