FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 302

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.27
8.1.28
302
Note: Programming the MTT to a value of 00h disables this function, which could cause starvation
CNF—ICH4 Configuration Register (HUB-PCI—D30:F0)
Offset Address:
Default Value:
MTT—Multi-Transaction Timer Register (HUB-PCI—D30:F0)
Offset Address:
Default Value:
MTT is an 8-bit register that controls the amount of time that the ICH4’s arbiter allows a PCI
initiator to perform multiple back-to-back transactions on the PCI bus. The ICH4’s MTT
mechanism is used to guarantee a fair share of the Primary PCI bandwidth to an initiator that
performs multiple back-to-back transactions to fragmented memory ranges (and as a consequence
it can not use long burst transfers).
The number of clocks programmed in the MTT represents the guaranteed time slice (measured in
PCI clocks) allotted to the current agent, after which the arbiter will grant another agent that is
requesting the bus. The MTT value must be programmed with 8 clock granularity in the same
manner as MLT. For example, if the MTT is programmed to 18h, then the selected value
corresponds to the time period of 24 PCI clocks.The default value of MTT is 20h (32 PCI clocks).
problems for some PCI master devices. Programming of the MTT to anything less than 16 clocks
will not allow the Grant-to-FRAME# latency to be 16 clocks. The MTT timer will timeout before
the Grant-to-FRAME# trigger causing a re-arbitration. MTT timer must be set to greater than 16
clocks.
15:14
12:10
Bit
7:2
13
9
8
1
0
Reserved
Prefetch Flush Enable - R/W. When set, this bit causes CPU to PCI logic to only deliver “Demand”
data for a delayed transaction if a CPU to PCI write has occurred since the delayed transaction was
initiated. This bit must be set by system BIOS.
Reserved
High Priority PCI Enable (HP_PCI_EN) — R/W.
0 = All PCI REQ#/GNT pairs have the same arbitration priority.
1 = Enables a mode where the REQ[0]#/GNT[0]# signal pair has a higher arbitration priority.
Hole Enable (15 MB–16 MB) — R/W.
0 = Disable
1 = Enables the 15 MB to 16 MB hole in main memory.
Reserved
12-Clock Retry Enable — R/W. System BIOS must set this bit for PCI compliance.
0 = If this bit is not set, the ICH4 will insert as many wait states as needed to complete the PCI to
0 = The ICH4 will retry a PCI to memory cycle (reads or writes) if the ICH4 is not able to complete
Reserved
memory cycle.
the transfer in 12 PCI clocks.
50–51h
1400h
70h
20h
Description
Attribute:
Size:
Attribute:
Size:
Intel
®
82801DBM ICH4-M Datasheet
R/W
16 bits
R/W
8 bits