FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 185

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

5.15.6
5.15.7
Intel
Warning:
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82801DBM ICH4-M Datasheet
Note: The internal Base Clock for Ultra ATA/100 (Mode 5) runs at 133 MHz, and the Cycle Time (CT)
Ultra ATA/33/66/100 Timing
The timings for Ultra ATA/33/66/100 modes are programmed via the Synchronous DMA Timing
Register and the IDE Configuration Register. Different timings can be programmed for each drive
in the system. The Base Clock frequency for each drive is selected in the IDE Configuration
Register. The Cycle Time (CT) and Ready to Pause (RP) time (defined as multiples of the Base
Clock) are programmed in the Synchronous DMA Timing Register. The Cycle Time represents the
minimum pulse width of the data strobe (STROBE) signal. The Ready to Pause time represents the
number of Base Clock periods that the ICH4 will wait from deassertion of DMARDY# to the
assertion of STOP when it desires to stop a burst read transaction.
must be set for three Base Clocks. The ICH4 will thus toggle the write strobe signal every 22.5 ns,
transferring two bytes of data on each strobe edge. This means that the ICH4 will perform Mode 5
write transfers at a maximum rate of 88.9 MB/s. For read transfers, the read strobe will be driven
by the ATA/100 device, and the ICH4 supports reads at the maximum rate of 100 MB/s.
IDE Swap Bay
To support a swap bay, the ICH4 allows the IDE output signals to be tri-stated and input buffers to
be turned off. This should be done prior to the removal of the drive. The output signals can also be
driven low. This can be used to remove charge built up on the signals. Configuration bits are
included in the IDE I/O Configuration Register, offset 54h in the IDE PCI configuration space.
In an IDE Hot Swap Operation, an IDE device is removed and a new one inserted while the IDE
interface is powered down and the rest of the system is in a fully powered-on state (SO). During an
IDE Hot Swap, if the operating system executes cycles to the IDE interface after it has been
powered down, it will cause the ICH4 to hang the system that is waiting for IORDY to be asserted
from the drive. To correct this issue, the following BIOS procedures are required for performing an
IDE hot swap.
The software should not attempt to control the outputs (either tri-state or driving low), while an
IDE transfer is in progress. Unpredictable results could occur, including a system lockup.
1. Program IDE SIG_MODE (offset 54h) to 10b (drive low mode).
2. Clear IORDY Sample Point Enable (bits 1 or 5 of IDE Timing register). This prevents ICH4
from waiting for IORDY assertion when the operating system accesses the IDE device after
the IDE drive powers down, and ensures that zeros will always be returned for read cycles that
occur during hot swap operation.
Functional Description
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