FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 475

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

13.1.4
13.1.5
13.1.6
Intel
®
82801DBM ICH4-M Datasheet
STA—Device Status Register (SMBUS—D31:F3)
Address:
Default Value:
REVID—Revision ID Register (SMBUS—D31:F3)
Offset Address:
Default Value:
SCC—Sub Class Code Register (SMBUS—D31:F3)
Address Offset:
Default Value:
7:0
Bit
10:9
Bit
4:0
15
14
13
12
11
7:0
Bit
8
7
6
5
Revision Identification Value — RO. Refer to the ICH4 Specification Update for the value of the
Revision ID Register.
Detected Parity Error (DPE) — RO. Reserved as 0.
Signaled System Error (SSE) — RO. Reserved as 0.
Received Master Abort (RMA) — RO. Reserved as 0.
Received Target Abort (RTA) — RO. Reserved as 0.
Signaled Target Abort (STA) — R/WC.
Set when the function is targeted with a transaction that the ICH4 terminates with a target abort.
Software resets STA to 0 by writing a 1 to this bit location.
DEVSEL# Timing Status (DEV_STS) — RO . This 2-bit field defines the timing for DEVSEL#
assertion for positive decode.
01 = Medium timing.
Data Parity Error Detected (DPED) — RO. Reserved as 0.
Fast Back to Back Capable (FB2BC) — RO. Reserved as 1.
User Definable Features (UDF) — RO. Reserved as 0.
66 MHz Capable (66MHZ_CAP) — RO. Reserved as 0.
Reserved
Sub Class Code — RO.
05h = SM Bus serial controller
06–07h
0280h
08h
See Bit Description
0Ah
05h
Description
Description
Description
Attributes:
Size:
Attribute:
Size:
Attributes:
Size:
SMBus Controller Registers (D31:F3)
RO R/WC
16 bits
RO
8 bits
RO
8 bits
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