FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 550

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Electrical Characteristics
550
Table 17-8. Clock Timings (Sheet 3 of 3)
NOTES:
1. The USBCLK is a 48 MHz that expects a 40/60% duty cycle.
2. USBCLK is a pass-thru clock that is not altered by the ICH4. This frequency tolerance specification is
3. The maximum high time (t18 Max) provide a simple guaranteed method for devices to detect bus idle
4. BITCLK Rise and Fall times are measured from 10%VDD and 90%VDD.
5. This specification includes pin-to-pin skew from the clock generator as well as board skew.
6. SUSCLK duty cycle can range from 30% minimum to 70% maximum.
f ac97
f ioap
Sym
required for USB 1.1 compliance and is affected by external elements such as the clock generator and the
system board.
conditions.
t22
t23
t24
t25
t26
t27
t28
t29
t30
t31
t32
t33
t34
t35
f hi
t1
t2
Operating Frequency
High time
Low time
Rise time
Fall time
Operating Frequency
Output Jitter
High time
Low time
Rise time
Fall time
Operating Frequency
High time
Low time
Rise time
Fall time
CLK66 leads PCICLK
Period
High Time
Parameter
I/O APIC Clock (APICCLK)
AC’97 Clock (BITCLK)
Hub Interface Clock
PCI Clock (PCICLK)
14.32
32.56
32.56
0.25
0.25
Min
1.0
1.0
2.0
2.0
6.0
6.0
1.0
12
12
30
12
12.288
Intel
66
33.33
48.84
48.84
Max
33.3
750
5.0
5.0
6.0
6.0
1.2
1.2
4.5
36
36
®
82801DBM ICH4-M Datasheet
Unit
MHz
MHz
MHz
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
4
5
Notes
Figure
17-1
Figure
17-1
Figure
17-1
Figure
17-1
Figure
17-1
Figure
17-1
Figure
17-1
Figure
17-1
Figure
17-1
Figure
17-1
Figure
17-1
Figure
17-1
Figure
17-1
Figure
17-1
Figure