FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 59

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

2.19
Intel
®
Table 2-19. Power and Ground Signals
82801DBM ICH4-M Datasheet
Power and Ground
Vcc3_3
Vcc1_5
VccHI
V5REF
HIREF
VccSus3_3
VccSus1_5
V5REF_Sus
VccLAN3_3
VccLAN1_5
VccRTC
VccPLL
VBIAS
V_CPU_IO
Vss
Name
3.3 V supply for core well I/O buffers. This power may be shut off in S3, S4, S5, or G3
states.
1.5 V supply for core well logic. This power may be shut off in S3, S4, S5, or G3 states.
1.5 V supply for Hub Interface 1.5 logic.
1.8 V supply for Hub Interface 1.0 logic.
This power may be shut off in S3, S4, S5 or G3 states.
Reference for 5 V tolerance on core well inputs. This power may be shut off in S3, S4,
S5 or G3 states.
Analog Input. Expected voltages are:
This power is shut off in S3, S4, S5, and G3 states.
3.3 V supply for resume well I/O buffers. This power is not expected to be shut off
unless the main battery is removed or completely drained and AC power is not
available.
1.5 V supply for resume well logic. This power is not expected to be shut off unless the
main battery is removed or completely drained and AC power is not available.
Reference for 5 V tolerance on resume well inputs. This power is not expected to be
shut off unless the main battery is removed or completely drained and AC power is not
available.
3.3 V supply for LAN Connect interface buffers. This is a separate power plane that
may or may not be powered in S3–S5 states depending upon the presence or absence
of AC power and network connectivity. This plane must be on in S0 and S1-M.
1.5 V supply for LAN Controller logic. This is a separate power plane that may or may
not be powered in S3–S5 states depending upon the presence or absence of AC
power and network connectivity. This plane must be on in S0 and S1-M.
3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well. This power is not
expected to be shut off unless the RTC battery is removed or completely drained.
NOTE: Implementations should not attempt to clear CMOS by using a jumper to pull
1.5 V supply for core well logic. This signal is used for the USB PLL. This power may
be shut off in S3, S4, S5, or G3 states.
RTC well bias voltage. The DC reference voltage applied to this pin sets a current that
is mirrored throughout the oscillator and buffer circuitry. See
Powered by the same supply as the processor I/O voltage. This supply is used to drive
the processor interface outputs.
Grounds.
• 0.9 V for HI 1.0 (Normal Hub Interface) Series Termination
• 350 mV for HI 1.5 (Enhanced Hub Interface) Parallel Termination
VccRTC low. Clearing CMOS in an ICH4-based platform can be done by
using a jumper on RTCRST# or GPI, or using SAFEMODE strap.
Description
Section
Signal Description
2.20.4.
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