FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 524

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

AC ’97 Modem Controller Registers (D31:F6)
524
Table 15-3. Modem Registers
Note: Internal reset as a result of D3
NOTE:
registers shared with the AC ’97 Audio Controller (GCR, GSR, CASR). All resume well registers
will not be reset by the D3
Core Well registers and bits NOT reset by the D3
Resume Well registers and bits will NOT be reset by the D3
1. MI = Modem in channel; MO = Modem out channel
•
•
•
•
Offset
3Ch
0Ah
0Bh
1Ah
1Bh
00h
04h
05h
06h
08h
10h
14h
15h
16h
18h
40h
44h
offset 3Ch
offset 40h
offset 44h – Codec Access Semaphore Register (CAS)
offset 40h
MO_BDBAR
GLOB_CNT
ACC_SEMA
MI_BDBAR
GLOB_STA
Mnemonic
MI_PICB
MI_PICB
MO_CIV
MO_PIV
MO_LVI
MO_SR
MO_CR
MI_CIV
MI_PIV
–
–
MI_LVI
MI_SR
MI_CR
–
43h – bits[29,15,11:10] Global Status (GLOB_STA)
43h – bits[17:16] Global Status (GLOB_STA)
3Fh – bits[6:0] Global Control (GLOB_CNT)
HOT
Modem In Buffer Descriptor List Base Address
Register
Modem In Current Index Value Register
Modem In Last Valid Index Register
Modem In Status Register
Modem In Position In Current Buffer Register
Modem In Prefetch Index Value Register
Modem In Control Register
Modem Out Buffer Descriptor List Base Address
Register
Modem Out Current Index Value Register
Modem Out Last Valid Register
Modem Out Status Register
Modem In Position In Current Buffer Register
Modem Out Prefetched Index Register
Modem Out Control Register
Global Control
Global Status
Codec Write Semaphore Register
HOT
to D0 transition.
to D0 transition will reset all the core well registers except the
Name
HOT
to D0 transition:
HOT
Intel
to D0 transition:
®
82801DBM ICH4-M Datasheet
00000000h
00000000h
00000000h
00000000h
Default
0001h
0001h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
RO, R/WC,
R/WC, RO
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO