FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 581

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
Table 19-3. XOR Chain 1
82801DBM ICH4-M Datasheet
Likewise, applying Vector 7 (all 1s) to the chain inputs (given that there are an even number of
input signals in the chain), will consistently produce a 1 at the XOR chain output on a good board.
One short to VSS (or open floating to VSS) will result in a 0 at the chain output, signaling a defect.
It is important to note that the number of inputs pulled to 1 will affect the expected chain output
value. If the number of chain inputs pulled to 1 is even, then expect 1 at the output. If the number of
chain inputs pulled to 1 is odd, expect 0 at the output.
Continuing with the example in
sequence, the XOR Output will toggle between 0 and 1. Any break in the toggling sequence
(e.g., 1011) will identify the location of the short or open.
NOTES:
1. RTCRST# asserted for 4 PCI clocks while PWROK active.
AC_SYNC
AC_SDOUT
PIRQE#/GPIO2
GNT2#
GNT3#
GNTA#/GPIO16
REQB#/REQ5#/
GPIO1
REQ4#
REQA#/GPIO0
PIRQF#/GPIO3
GNT4#
GNTB#/
GNT5#GPIO17
GNT1#
PIRQC#
PIRQA#
PIRQH#/GPIO5
PIRQD#
REQ1#
REQ2#
AD18
REQ0#
PIRQG#/GPIO4
AD28
PIRQB#
AD15
Pin Name
(1)
Ball #
C9
D9
C8
D7
D6
C5
D5
C4
C3
D3
C2
A7
B7
E8
A6
B6
B5
E6
B4
A3
A2
B3
E5
B1
F5
Top of XOR Chain
2nd signal in XOR
Table
Notes
19-2, as the input pins are driven to 1 across the chain in
GNT0#
AD22
AD30
AD20
AD16
AD4
AD24
AD0
STOP#
AD11
AD26
AD6
TRDY#
FRAME#
AD9
AD2
PAR
AD5
AD13
AD1
SERR#
C/BE0#
C/BE1#
AD3
AD10
BATLOW#
Pin Name
Ball #
AB2
C1
E4
D2
E3
G5
E2
H5
G4
E1
H4
G2
H3
G1
H2
K5
K4
K1
F4
F3
F2
F1
L1
J4
J3
J2
XOR Chain 1
OUTPUT
Notes
Testability
581