FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 468

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

EHCI Controller Registers (D29:F7)
12.2.3
12.2.3.1
468
Table 12-4. Debug Port Register Address Map
Note: Software should do Read-Modify-Write operations to this register to preserve the contents of bits
Note: To preserve the usage of RESERVED bits in the future, software should always write the same
USB 2.0-Based Debug Port Register
The Debug port’s registers are located in the same memory area, defined by the Base Address
Register (BAR), as the standard EHCI registers. The base offset for the debug port registers (80h)
is declared in the Debug Port Base Offset Capability Register at Configuration offset 5Ah. The
specific EHCI port that supports this debug capability is indicated by a 4-bit field (bits 20
the HCSPARAMS register of the EHCI controller.
The map of the Debug Port registers is shown in
below.
NOTES:
Control/Status Register
Offset:
Default Value:
not being modified. This include Reserved bits.
value read from the bit until it is defined. Reserved bits will always return 0 when read.
1. All of these registers are implemented in the core well and reset by PCIRST#, EHC HCRESET, and a EHC
2. The hardware associated with this register provides no checks to ensure that software programs the interface
Offset
D3-to-D0 transition
correctly. How the hardware behaves when programmed illegally is undefined.
Bit
31
30
29
0Ch
00h
04h
08h
10h
Reserved
OWNER_CNT — R/W.
0 = Default.
1 = Ownership of the debug port is forced to the EHCI controller (i.e., immediately taken away
Reserved
Control/Status
USB PIDs
Data Buffer (Bytes 3:0)
Data Buffer (Bytes 7:4)
Config Register
from the companion Classic USB Host Controller). If the port was already owned by the EHCI
controller, then setting this bit has no effect. This bit overrides all of the ownership-related bits
in the standard EHCI registers.
00h
00000000h
.
Register Name
Description
Table
Attribute:
Size:
12-4. Each register is defined individually
Intel
R/W, RO
32 bits
®
82801DBM ICH4-M Datasheet
R/W, RO
R/W, RO
–
23) in
Type
R/W
R/W
R/W