FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 502

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

AC ’97 Audio Controller Registers (D31:F5)
502
Table 14-2. Intel
NOTE:
The Bus Master registers are located from offset + 00h to offset + 51h and reside in the AC ‘97
controller. Accesses to these registers do NOT cause the cycle to be forwarded over the AC-link to
the codec. Software can access these registers as bytes, word, or DWord quantities, but reads must
not cross DWord boundaries.
In the case of the split codec implementation accesses to the different codecs are differentiated by
the controller by using address offsets 00h
for the secondary codec and address offsets 100h
The Global Control (GLOB_CNT) and Global Status (GLOB_STA) registers are aliased to the
same global registers in the audio and modem I/O space. Therefore a read/write to these registers in
either audio or modem I/O space affects the same physical register.
Bus Mastering registers exist in I/O space and reside in the AC ‘97 controller. The six channels,
PCM in, PCM in 2, PCM out, Mic in, Mic 2, and S/PDIF out, each have their own set of Bus
Mastering registers. The following register descriptions apply to all six channels. The register
definition section titles use a generic “x_” in front of the register to indicate that the register applies
to all six channels. The naming prefix convention used in
I/O address is as follows:
PI = PCM in channel
PO = PCM out channel
MC = Mic in channel.
MC2 = Mic 2 channel
PI2 = PCM in 2 channel
SP = S/PDIF out channel.
1. Software should not try to access reserved registers
2. Primary Codec ID cannot be changed. Secondary codec ID can be changed via bits 1:0 of configuration
3. The tertiary offset is only available through the memory space defined by the MMBAR register.
(Codec ID =00)
Primary Offset
register 40h. Tertiary codec ID can be changed via bits 3:2 of configuration register 40h.
3C–56h
®
3Ah
5Ah
7Ch
7Eh
38h
58h
ICH4 Audio Mixer Register Configuration (Sheet 2 of 2)
Secondary Offset
(Codec ID =01)
BC–D6h
BAh
D8h
DAh
FCh
FEh
B8h
–
7Fh for the primary codec, address offsets 80h
(Codec ID =10)
Tertiary Offset
13C–156h
–
17Ch
138h
13Ah
158h
15Ah
17Eh
17Fh for the tertiary codec.
Table 14-3
Intel
6Ch Vol: L, R Surround
S/PDIF Control
Intel RESERVED
AC ’97 Reserved
Vendor Reserved
Vendor ID1
Vendor ID2
®
NAMBAR Exposed Registers
82801DBM ICH4-M Datasheet
and in the register description
(D31:F5)
–
FFh