FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 421

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

11.1.4
11.1.5
11.1.6
Intel
®
82801DBM ICH4-M Datasheet
STA—Device Status Register (USB—D29:F0/F1/F2)
Address Offset:
Default Value:
RID—Revision Identification Register (USB—D29:F0/F1/F2)
Address Offset:
Default Value:
PI—Programming Interface (USB—D29:F0/F1/F2)
Address Offset:
Default Value:
15:14
10:9
4:0
Bit
13
12
Bit
7:0
Bit
7:0
11
8
7
6
5
Reserved as 00b. Read Only.
Received Master Abort (RMA) — R/WC.
0 = Software clears this bit by writing a 1 to the bit location.
1 = USB, as a master, generated a master-abort.
Reserved. Always read as 0.
Signaled Target Abort (STA) — R/WC.
0 = Software clears this bit by writing a 1 to the bit location.
1 = USB function is targeted with a transaction that the ICH4 terminates with a target abort.
DEVSEL# Timing Status (DEV_STS) — RO: This 2-bit field defines the timing for DEVSEL#
assertion. These read only bits indicate the ICH4's DEVSEL# timing when performing a positive
decode. ICH4 generates DEVSEL# with medium timing for USB.
Data Parity Error Detected (DPED) — RO. Reserved as 0.
Fast Back to Back Capable (FB2BC) — RO. Reserved as 1.
User Definable Features (UDF) — RO. Reserved as 0.
66 MHz Capable (66MHZ_CAP) — RO. Reserved as 0.
Reserved
Revision Identification Value — RO. Refer to the ICH4 Specification Update for the value of the
Revision ID Register.
Programming Interface — RO.
00h = No specific register level programming interface defined.
06
0280h
08h
See Bit Description
09h
00h
–
07h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
USB UHCI Controllers Registers
R/WC, RO
16 bits
RO
8 bits
RO
8 bits
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