FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 181

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
82801DBM ICH4-M Datasheet
Note: System BIOS must clear the Interrupt Status bit (bit-7) in Bus Master IDE Status Register for
The last PRD in a table has the End of List (EOL) bit set. The PCI bus master data transfers will
terminate when the physical region described by the last PRD in the table has been completely
transferred. The active bit in the Status Register will be reset and the DDRQ signal will be masked.
The buffer is flushed (when in the write state) or invalidated (when in the read state) when a
terminal count condition exists; that is, the current region descriptor has the EOL bit set and that
region has been exhausted. The buffer is also flushed (write state) or invalidated (read state) when
the Interrupt bit in the Bus Master IDE Status register is set. Software that reads the status register
and finds the Error bit reset, and either the Active bit reset or the Interrupt bit set, can be assured
that all data destined for system memory has been transferred and that data is valid in system
memory.
after a DMA transfer has started.
During concurrent DMA or Ultra ATA transfers, the ICH4 IDE interface arbitrates between the
primary and secondary IDE cables when a PRD expires.
BOTH primary and secondary channels before returning from an INT 13 read or write command.
This ensures that the pending IDE interrupt(s) are cleared before exiting the routine. The registers
are located in I/O space via BM_BASE register (Bus0:Device31:Function1:Register20-23h) ar
offset 02h and 0Ah respectively.
A System hang may occur if there exists a pending IDE interrupt status bit during Native IDE read/
write operations resulting in an apparent hang condition (Interrupt Storm).
5. Once the PRD is loaded internally, the IDE device receives a DMA acknowledge.
6. The controller transfers data to/from memory responding to DMA requests from the IDE
7. At the end of the transfer the IDE device signals an interrupt.
8. In response to the interrupt, software resets the Start/Stop bit in the command register. It then
visible by software, the Current Base and Current Count registers. These registers hold the
current value of the address and byte count loaded from the PRD table. The value in these
registers is only valid when there is an active command to an IDE device.
device. The IDE device and the host controller may or may not throttle the transfer several
times. When the last data transfer for a region has been completed on the IDE interface, the
next descriptor is fetched from the table. The descriptor contents are loaded into the Current
Base and Current Count registers.
reads the controller status followed by the drive status to determine if the transfer completed
successfully.
Table 5-54
describes how to interpret the Interrupt and Active bits in the Status Register
Functional Description
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