FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 481

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

13.2.3
13.2.4
13.2.5
Intel
®
82801DBM ICH4-M Datasheet
HST_CMD—Host Command Register
Register Offset:
Default Value:
XMIT_SLVA—Transmit Slave Address Register
Register Offset:
Default Value:
This register is transmitted by the host controller in the slave address field of the SMBus protocol.
HST_D0—Data 0 Register
Register Offset:
Default Value:
7:0
7:1
7:0
Bit
Bit
Bit
Bit
0
1
0
This 8-bit field is transmitted by the host controller in the command field of the SMBus protocol during
the execution of any command.
ADDRESS — R/W. 7-bit address of the targeted slave.
RW — R/W. Direction of the host transfer.
0 = Write
1 = Read
DATA0/COUNT — R/W. This field contains the eight bit data sent in the DATA0 field of the SMBus
protocol. For block write commands, this register reflects the number of bytes to transfer. This register
should be programmed to a value between 1 and 32 for block counts. A count of 0 or a count above 32
will result in unpredictable behavior. The host controller does not check or log illegal block counts.
KILL — R/W.
0 = Normal SMBus Host Controller functionality.
1 = When set, kills the current host transaction taking place, sets the FAILED status bit, and
INTREN — R/W.
0 = Disable.
1 = Enable the generation of an interrupt or SMI# upon the completion of the command.
asserts the interrupt (or SMI#). This bit, once set, must be cleared by software to allow the
SMBus Host Controller to function normally.
03h
00h
04h
00h
05h
00h
Description
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
SMBus Controller Registers (D31:F3)
R/W
8 bits
R/W
8 bits
R/W
8 bits
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