FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 601

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Table A-3. Intel
Intel
SCB Status Word
SCB Command Word
SCB General Pointer
PORT
EEPROM Control Register
MDI Control Register
Receive DMA Byte Count
Early Receive Interrupt
Flow Control Register
PMDR
General Control
General Status
PM1 Status
PM1 Enable
PM1 Control
PM1 Timer
Processor Control
Level 2 Register
Level 3 Register
Level 4 Register
PM2 Control
General Purpose Event 0 Status
General Purpose Event 0
Enables
SMI# Control and Enable
SMI Status Register
CSR_IO_BASE set in Section 7.1.12, “CSR_IO_BASE — CSR I/O-Mapped Base Address Register (LAN Controller—
®
“CSR_MEM_BASE CSR — Memory-Mapped Base Address Register (LAN Controller—B1:D8:F0)” on page 7-270
82801DBM ICH4-M Datasheet
LAN CSR at CSR_IO_BASE + Offset or CSR_MEM_BASE + Offset. CSR_MEM_BASE set in Section 7.1.11,
Register Name
PMBASE set in Section 9.1.10, “PMBASE—ACPI Base Address (LPC I/F—D31:F0)” on page 9-310
LAN Control/Status Registers (CSR) may be mapped to either I/O space or memory space.
®
ICH4 Variable I/O Registers (Sheet 1 of 6)
Power Management I/O Registers at PMBASE+Offset
OBh–08h
0Fh–0Eh
1Ah–19h
01h–00h
03h–02h
07h–04h
13h–10h
17h–14h
10h–13h
2C–2Fh
08–0Bh
28–2Bh
00–01h
02–03h
04–07h
30–31h
34–35h
Offset
1Ch
1Dh
1Bh
18h
14h
15h
16h
20h
B1:D8:F0)” on page 7-271
Section 7.2.1, “System Control Block Status Word Register” on page 7-276
Section 7.2.2, “System Control Block Command Word Register” on
page 7-278
Section 7.2.3, “System Control Block General Pointer Register” on
page 7-280
Section 7.2.4, “PORT Register” on page 7-280
Section 7.2.5, “EEPROM Control Register” on page 7-281
Section 7.2.6, “Management Data Interface (MDI) Control Register” on
page 7-282
Section 7.2.7, “Receive DMA Byte Count Register” on page 7-283
Section 7.2.8, “Early Receive Interrupt Register” on page 7-283
Section 7.2.9, “Flow Control Register” on page 7-284
Section 7.2.10, “Power Management Driver (PMDR) Register” on
page 7-285
Section 7.2.11, “General Control Register” on page 7-286
Section 7.2.12, “General Status Register” on page 7-286
Section 9.8.3.1, “PM1_STS—Power Management 1 Status Register” on
page 9-370
Section 9.8.3.2, “PM1_EN—Power Management 1 Enable Register” on
page 9-372
Section 9.8.3.3, “PM1_CNT—Power Management 1 Control Register” on
page 9-373
Section 9.8.3.4, “PM1_TMR—Power Management 1 Timer Register” on
page 9-374
Section 9.8.3.5, “PROC_CNT—Processor Control Register” on page 9-374
Section 9.8.3.6, “LV2 — Level 2 Register” on page 9-375
Section 9.8.3.7, “LV3—Level 3 Register” on page 9-376
Section 9.8.3.7, “LV3—Level 3 Register” on page 9-376
Section 9.8.3.9, “PM2_CNT—Power Management 2 Control” on page 9-376
Section 9.8.3.10, “GPE0_STS—General Purpose Event 0 Status Register”
on page 9-377
Section 9.8.3.11, “GPE0_EN—General Purpose Event 0 Enables Register”
on page 9-379
Section 9.8.3.12, “SMI_EN—SMI Control and Enable Register” on
page 9-380
Section 9.8.3.13, “SMI_STS—SMI Status Register” on page 9-382
Datasheet Location
Register Index
601