FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 510

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

AC ’97 Audio Controller Registers (D31:F5)
14.2.9
510
GLOB_STA—Global Status Register
I/O Address:
Default Value:
Lockable:
Reads across DWord boundaries are not supported.
31:30
Bit
29
28
27
26
25
Bit
2
1
0
Reserved.
AC_SDIN2 Resume Interrupt (S2RI)
AC_SDIN[2]. This bit is not affected by D3
0 = Cleared by writing a 1 to this bit position.
1 = Resume event occurred.
AC_SDIN2 Codec Ready (S2CR)
AC_SDIN[2]. Bus masters ignore the condition of the codec ready bits, so software must check this
bit before starting the bus masters. Once the codec is “ready”, it must never go “not ready”
spontaneously.
0 = Not Ready.
1 = Ready.
Bit Clock Stopped (BCS)
0 = Transition is found on BIT_CLK.
1 = ICH4 detects that there has been no transition on BIT_CLK for four consecutive PCI clocks.
S/PDIF Interrupt (SPINT)
0 = When the specific status bit is cleared, this bit will be cleared.
1 = Indicates that the S/PDIF out channel interrupt status bits have been set.
PCM In 2 Interrupt (P2INT)
0 = When the specific status bit is cleared, this bit will be cleared.
1 = Indicates that one of the PCM In 2 channel status bits have been set.
AC ’97 Warm Reset — R/W-Special.
0 = Normal operation.
1 = Writing a 1 to this bit causes a warm reset to occur on the AC-link. The warm reset will awaken
AC ’97 Cold Reset# — R/W.
0 = Writing a 0 to this bit causes a cold reset to occur throughout the AC ‘97 circuitry. All data in
1 = This bit defaults to 0 and hence after reset, the driver needs to set this bit to a 1. The value of
NOTE: This bit is in the Core well.
GPI Interrupt Enable (GIE) — R/W. This bit controls whether the change in status of any GPI
causes an interrupt.
0 = Bit 0 of the Global Status Register is set, but no interrupt is generated.
1 = The change on value of a GPI causes an interrupt and sets bit 0 of the Global Status Register.
a suspended codec without clearing its internal registers. If software attempts to perform a
warm reset while bit_clk is running, the write will be ignored and the bit will not change. This bit
is self-clearing (it remains set until the reset completes and bit_clk is seen on the ACLink, after
which it clears itself).
the controller and the codec will be lost. Software needs to clear this bit no sooner than the
minimum number of ms have elapsed.
this bit is retained after suspends; hence, if this bit is set to a 1 prior to suspending, a cold reset
is not generated automatically upon resuming.
00700000h
NABMBAR + 30h
No
—
—
—
RO. This bit indicates that the bit clock is not running.
RO.
RO.
—
—
RO. This bit reflects the state of the codec ready bit in
R/WC. This bit indicates that a resume event occurred on
HOT
Description
Description
to D0 Reset.
Attribute:
Size:
Power Well:
Intel
®
82801DBM ICH4-M Datasheet
RO, R/W, R/WC
32 bits
Core