FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 291

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

8.1.3
Intel
®
82801DBM ICH4-M Datasheet
CMD—Command Register (HUB-PCI—D30:F0)
Offset Address:
Default Value:
15:10
Bit
9
8
7
6
5
4
3
2
1
0
Reserved
Fast Back to Back Enable (FBE) — RO. Hardwired to 0. The ICH4 does not support this capability.
SERR# Enable (SERR_EN) — R/W.
0 = Disable.
1 = Enable the ICH4 to generate an NMI (or SMI# if NMI routed to SMI#) when the D30:F0 SSE bit
Wait Cycle Control (WCC) — RO. Hardwired to 0.
Parity Error Response (PER) — R/W.
0 = The ICH4 will ignore parity errors on the hub interface.
1 = The ICH4 is allowed to report parity errors detected on the hub interface.
VGA Palette Snoop (VPS) — RO. Hardwired to 0.
Memory Write and Invalidate Enable (MWIE) — RO. Hardwired to 0.
Special Cycle Enable (SCE) — RO. Hardwired to 0 by P2P Bridge spec.
Bus Master Enable (BME) — R/W.
0 = Disable
1 = Allows the Hub interface-to-PCI bridge to accept cycles from PCI to run on the hub interface.
NOTES:
Memory Space Enable (MSE) — R/W. The ICH4 provides this bit as read/writable for software
only. However, the ICH4 ignores the programming of this bit, and runs hub interface memory cycles
to PCI.
I/O Space Enable (IOSE) — R/W. The ICH4 provides this bit as read/writable for software only.
However, the ICH4 ignores the programming of this bit and runs hub interface I/O cycles to PCI that
are not intended for USB, IDE, or AC ’97.
1. This bit does not affect the CF8h and CFCh I/O accesses.
2. Cycles that generated from the ICH4’s Device 31 functionality are not blocked by clearing this
bit. (PC/PCI Cascade Mode cycles may be blocked)
(offset 06h, bit 14) is set.
04
0001h
–
05h
Hub Interface to PCI Bridge Registers (D30:F0)
Description
Attribute:
Size:
R/W, RO
16 bits
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