FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 89

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

5.2.2.7
5.2.3
Intel
®
Figure 5-5. 64-Word EEPROM Read Instruction Waveform
82801DBM ICH4-M Datasheet
Wake on LAN* (Preboot Wake-Up)
The LAN Controller enters Wake on LAN mode after reset if the Wake on LAN bit in the
EEPROM is set. At this point, the LAN Controller is in the D0u state.
When the LAN Controller is in Wake on LAN mode:
The LAN Controller switches from Wake on LAN mode to the D0a power state following a setup
of the Memory or I/O Base Address Registers in the PCI Configuration space.
Serial EEPROM Interface
The serial EEPROM stores configuration data for the ICH4 integrated LAN Controller and is a
serial in/serial out device. The LAN Controller supports a 64 register or 256 register size EEPROM
and automatically detects the EEPROM’s size. The EEPROM should operate at a frequency of at
least 1 MHz.
All accesses, either read or write, are preceded by a command instruction to the device. The
address field is six bits for a 64-register EEPROM or eight bits for a 256-register EEPROM. The
end of the address field is indicated by a dummy zero bit from the EEPROM, which indicates the
entire address field has been transferred to the device. An EEPROM read instruction waveform is
shown in
The LAN Controller performs an automatic read of seven words (0h, 1h, 2h, Ah, Bh, Ch and Dh) of
the EEPROM after the deassertion of Reset.
•
•
•
The LAN Controller scans incoming packets for a Magic Packet and asserts the PME# signal
for 52 ms when a one is detected in Wake on LAN mode.
The Activity LED changes its functionality to indicates that the received frame passed
Individual Address (IA) filtering or broadcast filtering.
The PCI Configuration registers are accessible to the host.
EE_DOUT
EE_SHCLKK
EE_CS
EE_DIN
Figure
5-5.
READ OP code
A
5
A
4
A
3
A
2
A
A
A
1
1
0
A
0
D
15
Functional Description
D
0
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