FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 522

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

AC ’97 Modem Controller Registers (D31:F6)
15.1.18
15.1.19
522
PC—Power Management Capabilities Register
(Modem—D31:F6)
Address Offset:
Default Value:
Lockable:
PCS—Power Management Control and Status Register
(Modem—D31:F6)
Address Offset:
Default Value:
Lockable:
This register is not affected by the D3
15:11
14:9
10:9
7:2
1:0
Bit
15
Bit
8:6
2:0
8
5
4
3
PME Status (PMES) — RW/C.
0 = Software clears this bit by writing a 1 to the bit position.
1 = This bit is set when the AC ’97 controller would normally assert the PME# signal independent of
Reserved — RO.
PME Enable (PMEE) — R/W. When set, and if corresponding PMES is also set, the AC'97 controller
sets the AC97_STS bit in the GPE0_STS register
Reserved — RO.
Power State — R/W. This field is used both to determine the current power state of the AC ’97
controller and to set a new power state. The values are:
00 = D0 state
01 = not supported
10 = not supported
11 = D3
When in the D3
memory spaces are not. Additionally, interrupts are blocked.
If software attempts to write a value of 10b or 01b in to this field, the write operation must complete
normally; however, the data is discarded and no state change occurs.
PME Support — RO. This field indicates PME# can be generated from all D states.
Reserved.
Auxiliary Current — RO. This field reports 375 mA maximum Suspend well current required when in
the D3cold state.
Device Specific Initialization (DSI) — RO. This bit indicates that no device-specific initialization is
required.
Reserved — RO.
PME Clock — RO. This bit indicates that PCI clock is not required to generate PME#.
Version — RO. This field indicates support for Revision 1.1 of the PCI Power Management
Specification.
the state of the PME_En bit. This bit resides in the resume well.
HOT
state
52h
C9C2h
54h
0000h
No
No
HOT
state, the AC ’97 controller’s configuration space is available, but the I/O and
HOT
to D0 transition.
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Intel
®
82801DBM ICH4-M Datasheet
RO
16 bits
Core
R/W, R/WC
16 bits
Resume