FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 77

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

5.1.6
5.1.6.1
5.1.6.2
Intel
®
Table 5-1. Type 0 Configuration Cycle Device Number Translation
82801DBM ICH4-M Datasheet
Note: Configuration writes to internal ICH4 USB EHCI (D29:F7) and AC ‘97 (D31:F5, F6) devices
Standard PCI Bus Configuration Mechanism
The PCI Bus defines a slot based “configuration space” that allows each device to contain up to
eight functions with each function containing up to 256, 8-bit configuration registers. The PCI
specification defines two bus cycles to access the PCI configuration space: Configuration Read and
Configuration Write. Memory and I/O spaces are supported directly by the processor.
Configuration space is supported by a mapping mechanism implemented within the ICH4. The PCI
specification defines two mechanisms to access configuration space, Mechanism #1 and
Mechanism #2. The ICH4 only supports Mechanism #1.
Configuration cycles for PCI Bus #0 devices #2 through #31, and for PCI Bus numbers greater than
0 will be sent towards the ICH4 from the host controller. The ICH4 compares the non-zero Bus
Number with the Secondary Bus Number and Subordinate Bus number registers of its PCI-to-PCI
bridge to determine if the configuration cycle is meant for Primary PCI or a downstream PCI bus.
when disabled are illegal and may cause undefined results.
Type 0 to Type 0 Forwarding
When a Type 0 configuration cycle is received on hub interface to any function other than USB
EHCI or AC ’97, the ICH4 forwards these cycles to PCI and then reclaims them. The ICH4 uses
address bits AD[15:13] to communicate the ICH4 device numbers in Type 0 configuration cycles.
If the Type 0 cycle on hub interface specifies any device number other than 29, 30 or 31, the ICH4
will not set any address bits in the range AD[31:11] during the corresponding transaction on PCI.
Table 5-1
The ICH4 logic will generate single DWord configuration read and write cycles on the PCI bus.
The ICH4 will generate a Type 0 configuration cycle for configurations to the bus number
matching the PCI bus. Type 1 configuration cycles will be converted to Type 0 cycles in this case.
If the cycle is targeting a device behind an external bridge, the ICH4 will run a Type 1 cycle on the
PCI bus.
Type 1 to Type 0 Conversion
When the bus number for the Type 1 configuration cycle matches the PCI (Secondary) bus number,
the ICH4 will convert the address as follows:
1. For device numbers 0 through 15, only one bit of the PCI address [31:16] will be set. If the
2. The ICH4 will always drive 0s on bits AD[15:11] when converting Type 1 configurations
3. Address bits [10:1] will also be passed unchanged to PCI.
4. Address bit 0 will be changed to 0.
Device # In Hub Interface Type 0 Cycle
device number is 0, AD[16] is set; if the device number is 1, AD[17] is set; etc.
cycles to Type 0 configuration cycles on PCI.
shows the device number translation.
0 through 28
29
30
31
AD[31:11] During Address Phase of Type 0 Cycle on PCI
0000000000000000_00000b
0000000000000000_00100b
0000000000000000_01000b
0000000000000000_10000b
Functional Description
77