FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 294

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.9
8.1.10
8.1.11
8.1.12
294
HEADTYP—Header Type Register (HUB-PCI—D30:F0)
Offset Address:
Default Value:
PBUS_NUM—Primary Bus Number Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
SBUS_NUM—Secondary Bus Number Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
SUB_BUS_NUM—Subordinate Bus Number Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
6:0
7:0
Bit
7:0
Bit
Bit
7:0
7
Bit
Multi-Function Device — RO. This bit is 0 to indicate a single function device.
Header Type — RO. 8-bit field identifies the header layout of the configuration space, which is a PCI-
to-PCI bridge in this case.
Primary Bus Number — RO. This field indicates the bus number of the hub interface and is
hardwired to 00h.
Secondary Bus Number — R/W. This field indicates the bus number of PCI. Note: when this
number is equal to the primary bus number (i.e., bus #0), the ICH4 will run hub interface configuration
cycles to this bus number as Type 1 configuration cycles on PCI.
Subordinate Bus Number — R/W. This field specifies the highest PCI bus number below the hub
interface to PCI bridge. If a Type 1 configuration cycle from the hub interface does not fall in the
Secondary-to-Subordinate Bus ranges of Device 30, the ICH4 will indicate a master abort back to
the hub interface.
18h
19h
1A
0Eh
01h
00h
00h
00h
Description
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Intel
®
82801DBM ICH4-M Datasheet
RO
8 bits
RO
8 bits
R/W
8 bits
R/W
8 bits