FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 272

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

LAN Controller Registers (B1:D8:F0)
7.1.15
7.1.16
7.1.17
7.1.18
272
CAP_PTR — Capabilities Pointer
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
INT_LN — Interrupt Line Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
INT_PN — Interrupt Pin Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
MIN_GNT — Minimum Grant Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
7:0
7:0
7:0
Bit
Bit
Bit
Bit
7:0
Capabilities Pointer (CAP_PTR) — RO. Hardwired to DCh; indicates the offset within
configuration space for the location of the Power Management registers.
Interrupt Line (INT_LN) — R/W. Identifies the system interrupt line to which the LAN Controller’s
PCI interrupt request pin (as defined in the Interrupt Pin Register) is routed.
Interrupt Pin (INT_PN) — RO. Hardwired to 01h to indicate that the LAN Controller’s interrupt
request is connected to PIRQA#. However, in the ICH4 implementation, when the LAN Controller
interrupt is generated PIRQ[E]# will go active, not PIRQ[A]#. Note that if the PIRQ[E]# signal is
used as a GPIO, the external visibility will be lost (though PIRQ[E]# will still go active internally).
Minimum Grant (MIN_GNT) — RO. This field indicates the amount of time (in increments of 0.25 µ s)
that the LAN Controller needs to retain ownership of the PCI bus when it initiates a transaction.
34h
3Dh
DCh
3Ch
00h
01h
3Eh
08h
Description
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Intel
®
82801DBM ICH4-M Datasheet
RO
8 bits
R/W
8 bits
RO
8 bits
RO
8 bits