FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 79

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

5.2.1.1
Intel
®
Figure 5-4. Integrated LAN Controller Block Diagram
82801DBM ICH4-M Datasheet
Parallel Subsystem Overview
The parallel subsystem is broken down into several functional blocks: a PCI bus master interface, a
micromachine processing unit and its corresponding microcode ROM, and a PCI Target Control/
EEPROM/ interface. The parallel subsystem also interfaces to the FIFO subsystem, passing data
(such as transmit, receive, and configuration data) and command and status parameters between
these two blocks.
The PCI bus master interface provides a complete interface to the PCI bus and is compliant with
the PCI Local Bus Specification, Revision 2.2. The LAN Controller provides 32 bits of addressing
and data, as well as the complete control interface to operate on the PCI bus. As a PCI target, it
follows the PCI configuration format which allows all accesses to the LAN Controller to be
automatically mapped into free memory and I/O space upon initialization of a PCI system. For
processing of transmit and receive frames, the integrated LAN Controller operates as a master on
the PCI bus, initiating zero wait-state transfers for accessing these data parameters.
The LAN Controller Control/Status Register Block is part of the PCI target element. The Control/
Status Register block consists of the following LAN Controller internal control registers: System
Control Block (SCB), PORT, EEPROM Control, and Management Data Interface (MDI) Control.
The micromachine is an embedded processing unit contained in the LAN Controller that enables
Adaptive Technology. The micromachine accesses the LAN Controller’s microcode ROM,
working its way through the opcodes (or instructions) contained in the ROM to perform its
functions. Parameters accessed from memory (e.g., pointers to data buffers) are also used by the
micromachine during the processing of transmit or receive frames by the LAN Controller. A
typical micromachine function is to transfer a data buffer pointer field to the LAN Controller’s
DMA unit for direct access to the data buffer. The micromachine is divided into two units, Receive
Unit and Command Unit which includes transmit functions. These two units operate independently
and concurrently. Control is switched between the two units according to the microcode instruction
flow. The independence of the Receive and Command units in the micromachine allows the LAN
Controller to execute commands and receive incoming frames simultaneously, with no real-time
processor intervention.
Interface
PCI
Data Interface Unit
Addressing Unit -
EEPROM Interface
Four Channel
Interface Unit
PCI Target and
PCI Bus
EEPROM
Interface
(BIU)
(DIU)
DMA
machine
Ported
Micro-
FIFO
Dual
FIFO Control
Rx FIFO
Tx FIFO
3 Kbyte
3 Kbyte
CSMA/CD
Unit
Functional Description
Interface
Connect
LAN
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