FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 113

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

5.7.1
5.7.1.1
5.7.1.2
Intel
®
Table 5-15. Interrupt Status Registers
Table 5-16. Content of Interrupt Vector Byte
82801DBM ICH4-M Datasheet
Interrupt Handling
Generating Interrupts
The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each interrupt
level. These bits are used to determine the interrupt vector returned, and status of any other pending
interrupts.
Acknowledging Interrupts
The processor generates an interrupt acknowledge cycle which is translated by the host bridge into
a PCI Interrupt Acknowledge Cycle to the ICH4. The PIC translates this command into two
internal INTA# pulses expected by the 8259 cores. The PIC uses the first internal INTA# pulse to
freeze the state of the interrupts for priority resolution. On the second INTA# pulse, the master or
slave will sends the interrupt vector to the processor with the acknowledged interrupt code. This
code is based upon bits [7:3] of the corresponding ICW2 register, combined with three bits
representing the interrupt within that controller.
IMR
IRR
ISR
Bit
Master, Slave Interrupt
Interrupt Request Register. This bit is set on a low-to-high transition of the interrupt line in edge
mode, and by an active high level in level mode. This bit is set whether or not the interrupt is
masked. However, a masked interrupt will not generate INTR.
Interrupt Service Register. This bit is set, and the corresponding IRR bit cleared, when an interrupt
acknowledge cycle is seen, and the vector returned is for that interrupt.
Interrupt Mask Register. This bit determines whether an interrupt is masked. Masked interrupts will
not generate INTR.
Table 5-15
IRQ7,15
IRQ6,14
IRQ5,13
IRQ4,12
IRQ2,10
IRQ3,11
IRQ1,9
IRQ0,8
defines the IRR, ISR and IMR.
Description
ICW2[7:3]
Bits [7:3]
Functional Description
Bits [2:0]
110
101
100
011
010
001
000
111
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