FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 559

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
Table 17-14. IOAPIC Bus Timing
Table 17-15. SMBus Timing
82801DBM ICH4-M Datasheet
NOTE: The Min AC column indicates the minimum times required by the SMBus and/or I
NOTES:
1. A device will timeout when any clock low exceeds this value.
2. t137 is the cumulative time a slave device is allowed to extend the clock cycles in one message from the
3. t138 is the cumulative time a master device is allowed to extend its clock cycles within each byte of a
4. t134 has a minimum timing for I
Sym
t130
t131
t132
t133
t134
t135
t136
t137
t138
Sym
t120
t121
t122
initial start to stop. If a slave device exceeds this time, it is expected to release both its clock and data lines
and reset itself.
message as defined from start-to-ack, ack-to-ack or ack-to-stop.
Bus Tree Time Between Stop and Start Condition
Hold Time after (repeated) Start Condition. After this
period, the first clock is generated.
Repeated Start Condition Setup Time
Stop Condition Setup Time
Data Hold Time
Data Setup Time
Device Time Out
Cumulative Clock Low Extend Time (slave device)
Cumulative Clock Low Extend Time (master device)
ICH4 tolerates these timings on both its SMBus and SMLink interfaces.
APICCD[1:0]# Valid Delay from APICCLK Rising
APICCD[1:0]# Setup Time to APICCLK Rising
APICCD[1:0]# Hold Time from APICCLK Rising
Parameter
Parameter
2
C of 0 ns, while the minimum timing for SMBus is 300 ns.
Min
3.0
8.5
3.0
Min
250
4.7
4.0
4.7
4.0
25
0
Max
12.0
Max
35
25
10
Electrical Characteristics
Units
ns
ns
ns
Units Notes
ms
ms
ms
µs
µs
µs
µs
ns
ns
2
C specifications. The
Notes
4
1
2
3
Figure
17-3
Figure
17-4
Figure
17-4
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Fig
17-17
17-17
17-17
17-17
17-17
17-17
17-17
17-17
Fig
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