FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 55

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

2.12
2.13
Intel
®
Table 2-11. Processor Interface Signals (Sheet 2 of 2)
Table 2-12. SM Bus Interface Signals
Table 2-13. System Management Interface Signals
82801DBM ICH4-M Datasheet
SMBus Interface
System Management Interface
RCIN#
A20GATE
CPUPWRGD
DPSLP#
SMBDATA
SMBCLK
SMBALERT#/
GPIO[11]
INTRUDER#
SMLINK[1:0]
Name
Name
Name
Type
Type
I/OD
I/OD
I/OD
Type
I
I
OD
O
I
I
SMBus Data: External pull-up is required.
SMBus Clock: External pull-up is required.
SMBus Alert: This signal is used to wake the system or generate SMI#. If not
used for SMBALERT#, it can be used as a GPI.
Intruder Detect: This signal can be set to disable the system if the box is detected
open. This signal’s status is readable, so it can be used like a GPI if the Intruder
Detection is not needed.
System Management Link: SMBus link to optional external system management
ASIC or LAN Controller. External pull-ups are required. Note that SMLINK[0]
corresponds to an SMBus Clock signal and SMLINK[1] corresponds to an SMBus
Data signal.
Keyboard Controller Reset CPU: The keyboard controller can generate INIT#
to the processor. This saves the external OR gate with the ICH4’s other sources
of INIT#. When the ICH4 detects the assertion of this signal, INIT# is generated
for 16 PCI clocks.
NOTE: The ICH4 ignores RCIN# assertion during transitions to the S1-M, S3,
A20 Gate: A20GATE is from the keyboard controller. The signal acts as an
alternative method to force the A20M# signal active. It saves the external OR
gate needed with various other PCIsets.
CPU Power Good: This signal should be connected to the processor’s
PWRGOOD input. To allow for Intel
signal is kept high during an Intel SpeedStep technology state transition to
prevent loss of processor context. This is an open-drain output signal (external
pull-up resistor required) that represents a logical AND of the ICH4’s PWROK
and VGATE / VRMPWRGD signals.
Deeper Sleep: This signal is asserted by the ICH4 to the processor. When the
signal is low, the processor enters the Deeper Sleep state by gating off the
processor Core clock inside the processor. When the signal is high (default),
the processor is not in the Deeper Sleep state. This signal behaves identically
to the STP_CPU# signal, but at the processor voltage level.
S4 and S5 states.
Description
Description
Description
®
SpeedStep™ technology support, this
Signal Description
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