FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 139

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

5.11.2
Intel
®
Table 5-32. Frequency Strap Behavior Based on Exit State
Table 5-33. Frequency Strap Bit Mapping
Figure 5-13. Signal Strapping
82801DBM ICH4-M Datasheet
Speed Strapping for Processor
The ICH4 directly sets the speed straps for the processor, saving the external logic that has been
needed with prior PCIsets. Refer to processor specification for speed strapping definition.
The ICH4 performs the following to set the speed straps for the processor:
NOTE: The FREQ_STRAP register is in the RTC well. The value in the register can be forced to 1111h via a
S3, S4, S5,
1. While PCIRST# is active, the ICH4 drives A20M#, IGNNE#, NMI, and INTR high.
2. As soon as PWROK goes active, the ICH4 reads the FREQ_STRAP field contents.
3. The next step depends on the power state being exited as described in
Exiting
or G3
State
S1-M
A20M#, IGNNE#,
pinstrap (AC_SDOUT signal), or the ICH4 can automatically force the speed strapping to 1111h if the
processor fails to boot.
INTR, NMI
Processor
FREQ_STRAP Bits [3:0]
There is no processor reset, so no frequency strap logic is used.
Based on PWROK going active, the ICH4 will deassert PCIRST#, and based on the value of the
FREQ_STRAP field (D31:F0,Offset D5h (BACK_CNTL)), the ICH4 will drive the intended core
frequency values on A20M#, IGNNE#, NMI, and INTR.
3
2
1
0
INIT#
CPURST#
Sets High/Low Level for the Corresponding Signal
4x 2 to 1
Mux
ICH4
Host Controller
ICH4
PCIRST#
Strap Register
IGNNE#
Frequency
A20M#
INTR
NMI
Functional Description
Table
5-32.
PWROK
139