FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 525

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

15.2.1
15.2.2
15.2.3
Intel
®
82801DBM ICH4-M Datasheet
x_BDBAR—Buffer Descriptor List Base Address Register
I/O Address:
Default Value:
Lockable:
Software can read the register at offset 00h by performing a single 32-bit read from address offset
00h. Reads across DWord boundaries are not supported.
x_CIV—Current Index Value Register
I/O Address:
Default Value:
Lockable:
Software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single,
32-bit read from address offset 04h. Software can also read this register individually by doing a
single, 8-bit read to offset 04h. Reads across DWord boundaries are not supported.
x_LVI—Last Valid Index Register
I/O Address:
Default Value:
Software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single,
32-bit read from address offset 04h. Software can also read this register individually by doing a
single, 8-bit read to offset 05h. Reads across DWord boundaries are not supported.
31:3
Bit
2:0
Bit
7:5
4:0
Bit
7:5
4:0
Buffer Descriptor List Base Address [31:3] — R/W. These bits represent address bits 31:3. The
entries should be aligned on 8-byte boundaries.
Hardwired to 0.
Hardwired to 0.
Current Index Value [4:0] — RO. These bits represent which buffer descriptor within the list of 16
descriptors is being processed currently. As each descriptor is processed, this value is
incremented.
Hardwired to 0
Last Valid Index [4:0] — R/W. These bits indicate the last valid descriptor in the list. This value is
updated by the software as it prepares new buffers and adds to the list.
MBAR + 00h (MIBDBAR),
MBAR + 10h (MOBDBAR)
00000000h
No
MBAR + 04h (MICIV),
MBAR + 14h (MOCIV),
00h
No
MBAR + 05h (MILVI),
MBAR + 15h (MOLVI)
00h
Description
Description
Description
AC ’97 Modem Controller Registers (D31:F6)
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Attribute:
Power Well:
R/W
32 bits
Core
RO
8 bits
Core
R/W
Core
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