FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 134

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.10.2
5.10.3
5.10.4
5.10.5
134
Interrupts
The real-time clock interrupt is internally routed within the ICH4 both to the I/O APIC and the
8259. It is mapped to interrupt vector 8. This interrupt does not leave the ICH4, nor is it shared with
any other interrupt. IRQ8# from the SERIRQ stream is ignored.
Lockable RAM Ranges
The RTC’s battery-backed RAM supports two 8-byte ranges that can be locked via the
configuration space. If the locking bits are set, the corresponding range in the RAM will not be
readable or writable. A write cycle to those locations will have no effect. A read cycle to those
locations will not return the location’s actual value (may be all 0s or all 1s).
Once a range is locked, the range can be unlocked only by a hard reset, which will invoke the BIOS
and allow it to relock the RAM range.
Century Rollover
The ICH4 detects a rollover when the Year byte (RTC I/O space, index offset 09h) transitions form
99 to 00. Upon detecting the rollover, the ICH4 will set the NEWCENTURY_STS bit
(TCOBASE + 04h, bit 7). If the system is in an S0 state, this will cause an SMI#. The SMI#
handler can update registers in the RTC RAM that are associated with century value. If the system
is in a sleep state (S1-M–S5) when the century rollover occurs, the ICH4 will also set the
NEWCENTURY_STS bit, but no SMI# is generated. When the system resumes from the sleep
state, BIOS should check the NEWCENTURY_STS bit and update the century value in the RTC
RAM.
Clearing Battery-Backed RTC RAM
Clearing CMOS RAM in an ICH4-based platform can be done by using a jumper on RTCRST# or
GPI, or using SAFEMODE strap. Implementations should not attempt to clear CMOS by using a
jumper to pull VccRTC low.
Using RTCRST# to clear CMOS
A jumper on RTCRST# can be used to clear CMOS values, as well as reset to default, the state of
those configuration bits that reside in the RTC power well. When the RTCRST# is strapped to
ground, the RTC_PWR_STS bit (D31:F0:A4h bit 2) is set and those configuration bits in the RTC
power well will be set to their default state. BIOS can monitor the state of this bit and manually
clear the RTC CMOS array once the system is booted. The normal position would cause RTCRST#
to be pulled up through a weak pull-up resistor.
state when RTCRST# is asserted.
Table 5-29
shows which bits are set to their default
Intel
®
82801DBM ICH4-M Datasheet