FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 593

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Table A-1. Intel
Intel
FWH Select 2 Register
FWH Decode Enable 2 Register
Function Disable Register
General Power Management
Configuration 1
General Power Management
Configuration 2
General Power Management
Configuration 3
Stop Clock Delay Register
GPI_ROUT
I/O Monitor [4:7] Trap Range Registers
I/O Monitor [4:7] Trap Mask Register
Vendor ID
Device ID
Command Register
Device Status
Revision ID Register
Programming Interface
Sub Class Code
Base Class Code
Master Latency Timer
Primary Command Block Base
Address Register
Primary Control Block Base Address
Register
Secondary Command Block Base
Address Register
I/O Monitor Trap Forwarding Enable
®
82801DBM ICH4-M Datasheet
Register Name
Register
®
ICH4 PCI Configuration Registers (Sheet 5 of 10)
C4h, C6h,
C8h, CAh
00h–01h
02h–03h
04h–05h
06h–07h
EE–EFh
B8–BBh
18–1Bh
10–13h
14–17h
Offset
CCh
A0h
A2h
A4h
A8h
C0h
0Ah
0Bh
0Dh
F0h
F2h
08h
09h
IDE Controller (D31:F1)
Section 9.1.34, “FWH_SEL2—FWH Select 2 Register (LPC I/F—D31:F0)”
on page 9-326
Section 9.1.35, “FWH_DEC_EN2—FWH Decode Enable 2 Register (LPC
I/F—D31:F0)” on page 9-327
Section 9.1.36, “FUNC_DIS—Function Disable Register (LPC I/F—
D31:F0)” on page 9-328
Section 9.8.1.1, “GEN_PMCON_1—General PM Configuration 1 Register
(PM—D31:F0)” on page 9-362
Section 9.8.1.2, “GEN_PMCON_2—General PM Configuration 2 Register
(PM—D31:F0)” on page 9-363
Section 9.8.1.3, “GEN_PMCON_3—General PM Configuration 3 Register
(PM—D31:F0)” on page 9-364
Section 9.8.1.4, “STPCLK_DEL—Stop Clock Delay Register (PM—
D31:F0)” on page 9-365
Section 9.8.1.5, “GPI_ROUT—GPI Routing Control Register (PM—
D31:F0)” on page 9-365
Section 9.8.1.6, “TRP_FWD_EN—IO Monitor Trap Forwarding Enable
Register (PM—D31:F0)” on page 9-366
Section 9.8.1.7, “MON[n]_TRP_RNG—I/O Monitor [4:7] Trap Range
Register for Devices 4–7 (PM—D31:F0)” on page 9-367
Section 9.8.1.8, “MON_TRP_MSK—I/O Monitor Trap Range Mask
Register for Devices 4–7 (PM—D31:F0)” on page 9-367
Section 10.1.1, “VID—Vendor ID Register (LPC I/F—D31:F1)” on
page 10-402
Section 10.1.2, “DID—Device ID Register (LPC I/F—D31:F1)” on
page 10-402
Section 10.1.3, “CMD — Command Register (IDE—D31:F1)” on
page 10-402
Section 10.1.4, “STS — Device Status Register (IDE—D31:F1)” on
page 10-403
Section 10.1.5, “REVID—Revision ID Register (IDE—D31:F1)” on
page 10-403
Section 10.1.6, “PI — Programming Interface Register (IDE—D31:F1)” on
page 10-404
Section 10.1.7, “SCC — Sub Class Code Register (IDE—D31:F1)” on
page 10-404
Section 10.1.8, “BCC — Base Class Code Register (IDE—D31:F1)” on
page 10-404
Section 10.1.9, “MLT — Master Latency Timer Register (IDE—D31:F1)”
on page 10-405
Section 10.1.10, “PCMD_BAR—Primary Command Block Base Address
Register (IDE—D31:F1)” on page 10-405
Section 10.1.11, “PCNL_BAR—Primary Control Block Base Address
Register (IDE—D31:F1)” on page 10-405
Section 10.1.12, “SCMD_BAR—Secondary Command Block Base
Address Register (IDE D31:F1)” on page 10-406
Datasheet Location
Register Index
593